| /external/llvm-project/llvm/utils/TableGen/ |
| D | InfoByHwMode.h | 36 DefaultMode = CodeGenHwModes::DefaultMode, enumerator
51 if (M != DefaultMode) in union_modes()
56 V.push_back(DefaultMode); in union_modes()
84 bool hasDefault() const { return hasMode(DefaultMode); } in hasDefault()
88 assert(hasMode(DefaultMode)); in get()
89 Map.insert({Mode, Map.at(DefaultMode)}); in get()
95 if (Mode != DefaultMode && F == Map.end()) in get()
96 F = Map.find(DefaultMode); in get()
103 return Map.size() == 1 && Map.begin()->first == DefaultMode; in isSimple()
114 Map.insert(std::make_pair(DefaultMode, I)); in makeSimple()
[all …]
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| D | RegisterBankEmitter.cpp | 88 else if (RCWithLargestRegsSize->RSI.get(DefaultMode).SpillSize < in addRegisterClass()
89 RC->RSI.get(DefaultMode).SpillSize) in addRegisterClass()
250 unsigned Size = RC.RSI.get(DefaultMode).SpillSize; in emitBaseClassImplementation()
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| D | CodeGenHwModes.h | 43 enum : unsigned { DefaultMode = 0 }; enumerator
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| D | InfoByHwMode.cpp | 27 if (Mode == DefaultMode) in getModeName()
69 auto D = Map.find(DefaultMode); in getOrCreateTypeForMode()
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| D | CodeGenHwModes.cpp | 81 return DefaultMode; in getHwModeId()
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| D | CodeGenDAGPatterns.cpp | 121 if (DefaultMode == M) { in insert()
143 if (M == DefaultMode || hasMode(M)) in constrain()
145 Map.insert({M, Map.at(DefaultMode)}); in constrain()
758 const TypeSetByHwMode::SetType &LegalTypes = Legal.get(DefaultMode); in expandOverloads()
821 TypeSetByHwMode::SetType &LegalTypes = LegalCache.getOrCreate(DefaultMode); in getLegalTypes()
1715 if (S.get(DefaultMode).empty()) in setDefaultMode()
4334 if (M == DefaultMode) in ExpandHwModeBasedTypes()
4348 if (M == DefaultMode) in ExpandHwModeBasedTypes()
4353 bool HasDefault = Modes.count(DefaultMode); in ExpandHwModeBasedTypes()
4355 AppendPattern(P, DefaultMode); in ExpandHwModeBasedTypes()
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| D | CodeGenDAGPatterns.h | 226 return Map.size() == 1 && Map.begin()->first == DefaultMode; in isDefaultOnly()
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| D | CodeGenRegisters.cpp | 801 RSI.Map.insert({DefaultMode, RI}); in CodeGenRegisterClass()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.td | 285 def VecI1: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
287 def VecI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
289 def VecI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
291 def VecI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
294 def VecPI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
296 def VecPI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
298 def VecPI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
301 def VecQ8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
303 def VecQ16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
305 def VecQ32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVRegisterInfo.td | 86 def XLenVT : ValueTypeByHwMode<[RV32, RV64, DefaultMode],
100 [RV32, RV64, DefaultMode],
106 [RV32, RV64, DefaultMode],
121 [RV32, RV64, DefaultMode],
134 [RV32, RV64, DefaultMode],
143 [RV32, RV64, DefaultMode],
156 [RV32, RV64, DefaultMode],
162 [RV32, RV64, DefaultMode],
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.td | 321 def VecI1: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
323 def VecI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
325 def VecI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
327 def VecI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
330 def VecPI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
332 def VecPI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
334 def VecPI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
337 def VecQ8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
339 def VecQ16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
341 def VecQ32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
[all …]
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| /external/llvm-project/llvm/test/TableGen/ |
| D | HwModeSelect.td | 24 def BadDef : ValueTypeByHwMode<[TestMode1, TestMode2, DefaultMode],
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIModeRegister.cpp | 130 unsigned DefaultMode = FP_ROUND_ROUND_TO_NEAREST; member in __anon2d8e8e840111::SIModeRegister
132 Status(FP_ROUND_MODE_DP(0x3), FP_ROUND_MODE_DP(DefaultMode));
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIModeRegister.cpp | 132 unsigned DefaultMode = FP_ROUND_ROUND_TO_NEAREST; member in __anon239725100111::SIModeRegister
134 Status(FP_ROUND_MODE_DP(0x3), FP_ROUND_MODE_DP(DefaultMode));
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| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCV.td | 192 defvar RV32 = DefaultMode;
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | Target.td | 36 def DefaultMode : HwMode<"">;
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| /external/llvm-project/llvm/include/llvm/Target/ |
| D | Target.td | 36 def DefaultMode : HwMode<"">;
|