1//===-- RISCV.td - Describe the RISCV Target Machine -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9include "llvm/Target/Target.td" 10 11//===----------------------------------------------------------------------===// 12// RISC-V subtarget features and instruction predicates. 13//===----------------------------------------------------------------------===// 14 15def FeatureStdExtM 16 : SubtargetFeature<"m", "HasStdExtM", "true", 17 "'M' (Integer Multiplication and Division)">; 18def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">, 19 AssemblerPredicate<(all_of FeatureStdExtM), 20 "'M' (Integer Multiplication and Division)">; 21 22def FeatureStdExtA 23 : SubtargetFeature<"a", "HasStdExtA", "true", 24 "'A' (Atomic Instructions)">; 25def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">, 26 AssemblerPredicate<(all_of FeatureStdExtA), 27 "'A' (Atomic Instructions)">; 28 29def FeatureStdExtF 30 : SubtargetFeature<"f", "HasStdExtF", "true", 31 "'F' (Single-Precision Floating-Point)">; 32def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">, 33 AssemblerPredicate<(all_of FeatureStdExtF), 34 "'F' (Single-Precision Floating-Point)">; 35 36def FeatureStdExtD 37 : SubtargetFeature<"d", "HasStdExtD", "true", 38 "'D' (Double-Precision Floating-Point)", 39 [FeatureStdExtF]>; 40def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">, 41 AssemblerPredicate<(all_of FeatureStdExtD), 42 "'D' (Double-Precision Floating-Point)">; 43 44def FeatureExtZfh 45 : SubtargetFeature<"experimental-zfh", "HasStdExtZfh", "true", 46 "'Zfh' (Half-Precision Floating-Point)", 47 [FeatureStdExtF]>; 48def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">, 49 AssemblerPredicate<(all_of FeatureExtZfh), 50 "'Zfh' (Half-Precision Floating-Point)">; 51 52def FeatureStdExtC 53 : SubtargetFeature<"c", "HasStdExtC", "true", 54 "'C' (Compressed Instructions)">; 55def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">, 56 AssemblerPredicate<(all_of FeatureStdExtC), 57 "'C' (Compressed Instructions)">; 58 59def FeatureExtZbb 60 : SubtargetFeature<"experimental-zbb", "HasStdExtZbb", "true", 61 "'Zbb' (Base 'B' Instructions)">; 62def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">, 63 AssemblerPredicate<(all_of FeatureExtZbb), 64 "'Zbb' (Base 'B' Instructions)">; 65 66def FeatureExtZbc 67 : SubtargetFeature<"experimental-zbc", "HasStdExtZbc", "true", 68 "'Zbc' (Carry-Less 'B' Instructions)">; 69def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">, 70 AssemblerPredicate<(all_of FeatureExtZbc), 71 "'Zbc' (Carry-Less 'B' Instructions)">; 72 73def FeatureExtZbe 74 : SubtargetFeature<"experimental-zbe", "HasStdExtZbe", "true", 75 "'Zbe' (Extract-Deposit 'B' Instructions)">; 76def HasStdExtZbe : Predicate<"Subtarget->hasStdExtZbe()">, 77 AssemblerPredicate<(all_of FeatureExtZbe), 78 "'Zbe' (Extract-Deposit 'B' Instructions)">; 79 80def FeatureExtZbf 81 : SubtargetFeature<"experimental-zbf", "HasStdExtZbf", "true", 82 "'Zbf' (Bit-Field 'B' Instructions)">; 83def HasStdExtZbf : Predicate<"Subtarget->hasStdExtZbf()">, 84 AssemblerPredicate<(all_of FeatureExtZbf), 85 "'Zbf' (Bit-Field 'B' Instructions)">; 86 87def FeatureExtZbm 88 : SubtargetFeature<"experimental-zbm", "HasStdExtZbm", "true", 89 "'Zbm' (Matrix 'B' Instructions)">; 90def HasStdExtZbm : Predicate<"Subtarget->hasStdExtZbm()">, 91 AssemblerPredicate<(all_of FeatureExtZbm), 92 "'Zbm' (Matrix 'B' Instructions)">; 93 94def FeatureExtZbp 95 : SubtargetFeature<"experimental-zbp", "HasStdExtZbp", "true", 96 "'Zbp' (Permutation 'B' Instructions)">; 97def HasStdExtZbp : Predicate<"Subtarget->hasStdExtZbp()">, 98 AssemblerPredicate<(all_of FeatureExtZbp), 99 "'Zbp' (Permutation 'B' Instructions)">; 100 101def FeatureExtZbr 102 : SubtargetFeature<"experimental-zbr", "HasStdExtZbr", "true", 103 "'Zbr' (Polynomial Reduction 'B' Instructions)">; 104def HasStdExtZbr : Predicate<"Subtarget->hasStdExtZbr()">, 105 AssemblerPredicate<(all_of FeatureExtZbr), 106 "'Zbr' (Polynomial Reduction 'B' Instructions)">; 107 108def FeatureExtZbs 109 : SubtargetFeature<"experimental-zbs", "HasStdExtZbs", "true", 110 "'Zbs' (Single-Bit 'B' Instructions)">; 111def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">, 112 AssemblerPredicate<(all_of FeatureExtZbs), 113 "'Zbs' (Single-Bit 'B' Instructions)">; 114 115def FeatureExtZbt 116 : SubtargetFeature<"experimental-zbt", "HasStdExtZbt", "true", 117 "'Zbt' (Ternary 'B' Instructions)">; 118def HasStdExtZbt : Predicate<"Subtarget->hasStdExtZbt()">, 119 AssemblerPredicate<(all_of FeatureExtZbt), 120 "'Zbt' (Ternary 'B' Instructions)">; 121 122// Some instructions belong to both the basic and the permutation 123// subextensions. They should be enabled if either has been specified. 124def HasStdExtZbbOrZbp 125 : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp()">, 126 AssemblerPredicate<(any_of FeatureExtZbb, FeatureExtZbp)>; 127def NotHasStdExtZbbOrZbp 128 : Predicate<"!(Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp())">; 129 130def FeatureExtZbproposedc 131 : SubtargetFeature<"experimental-zbproposedc", "HasStdExtZbproposedc", "true", 132 "'Zbproposedc' (Proposed Compressed 'B' Instructions)">; 133def HasStdExtZbproposedc : Predicate<"Subtarget->hasStdExtZbproposedc()">, 134 AssemblerPredicate<(all_of FeatureExtZbproposedc), 135 "'Zbproposedc' (Proposed Compressed 'B' Instructions)">; 136 137def FeatureStdExtB 138 : SubtargetFeature<"experimental-b", "HasStdExtB", "true", 139 "'B' (Bit Manipulation Instructions)", 140 [FeatureExtZbb, 141 FeatureExtZbc, 142 FeatureExtZbe, 143 FeatureExtZbf, 144 FeatureExtZbm, 145 FeatureExtZbp, 146 FeatureExtZbr, 147 FeatureExtZbs, 148 FeatureExtZbt]>; 149def HasStdExtB : Predicate<"Subtarget->hasStdExtB()">, 150 AssemblerPredicate<(all_of FeatureStdExtB), 151 "'B' (Bit Manipulation Instructions)">; 152 153def FeatureNoRVCHints 154 : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false", 155 "Disable RVC Hint Instructions.">; 156def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">, 157 AssemblerPredicate<(all_of(not FeatureNoRVCHints)), 158 "RVC Hint Instructions">; 159 160def FeatureStdExtV 161 : SubtargetFeature<"experimental-v", "HasStdExtV", "true", 162 "'V' (Vector Instructions)", 163 [FeatureStdExtF]>; 164def HasStdExtV : Predicate<"Subtarget->hasStdExtV()">, 165 AssemblerPredicate<(all_of FeatureStdExtV), 166 "'V' (Vector Instructions)">; 167 168def FeatureStdExtZvlsseg 169 : SubtargetFeature<"experimental-zvlsseg", "HasStdExtZvlsseg", "true", 170 "'Zvlsseg' (Vector segment load/store instructions)", 171 [FeatureStdExtV]>; 172def HasStdExtZvlsseg : Predicate<"Subtarget->hasStdExtZvlsseg()">, 173 AssemblerPredicate<(all_of FeatureStdExtZvlsseg), 174 "'Zvlsseg' (Vector segment load/store instructions)">; 175def FeatureExtZvamo 176 : SubtargetFeature<"experimental-zvamo", "HasStdExtZvamo", "true", 177 "'Zvamo'(Vector AMO Operations)", 178 [FeatureStdExtV]>; 179def HasStdExtZvamo : Predicate<"Subtarget->hasStdExtZvamo()">, 180 AssemblerPredicate<(all_of FeatureExtZvamo), 181 "'Zvamo'(Vector AMO Operations)">; 182 183def Feature64Bit 184 : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">; 185def IsRV64 : Predicate<"Subtarget->is64Bit()">, 186 AssemblerPredicate<(all_of Feature64Bit), 187 "RV64I Base Instruction Set">; 188def IsRV32 : Predicate<"!Subtarget->is64Bit()">, 189 AssemblerPredicate<(all_of (not Feature64Bit)), 190 "RV32I Base Instruction Set">; 191 192defvar RV32 = DefaultMode; 193def RV64 : HwMode<"+64bit">; 194 195def FeatureRV32E 196 : SubtargetFeature<"e", "IsRV32E", "true", 197 "Implements RV32E (provides 16 rather than 32 GPRs)">; 198def IsRV32E : Predicate<"Subtarget->isRV32E()">, 199 AssemblerPredicate<(all_of FeatureRV32E)>; 200 201def FeatureRelax 202 : SubtargetFeature<"relax", "EnableLinkerRelax", "true", 203 "Enable Linker relaxation.">; 204 205foreach i = {1-31} in 206 def FeatureReserveX#i : 207 SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]", 208 "true", "Reserve X"#i>; 209 210def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore", 211 "true", "Enable save/restore.">; 212 213//===----------------------------------------------------------------------===// 214// Named operands for CSR instructions. 215//===----------------------------------------------------------------------===// 216 217include "RISCVSystemOperands.td" 218 219//===----------------------------------------------------------------------===// 220// Registers, calling conventions, instruction descriptions. 221//===----------------------------------------------------------------------===// 222 223include "RISCVSchedule.td" 224include "RISCVRegisterInfo.td" 225include "RISCVCallingConv.td" 226include "RISCVInstrInfo.td" 227include "RISCVRegisterBanks.td" 228include "RISCVSchedRocket.td" 229include "RISCVSchedSiFive7.td" 230 231//===----------------------------------------------------------------------===// 232// RISC-V processors supported. 233//===----------------------------------------------------------------------===// 234 235def : ProcessorModel<"generic-rv32", NoSchedModel, []>; 236def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>; 237 238def : ProcessorModel<"rocket-rv32", RocketModel, []>; 239def : ProcessorModel<"rocket-rv64", RocketModel, [Feature64Bit]>; 240 241def : ProcessorModel<"sifive-7-rv32", SiFive7Model, []>; 242def : ProcessorModel<"sifive-7-rv64", SiFive7Model, [Feature64Bit]>; 243 244def : ProcessorModel<"sifive-e31", RocketModel, [FeatureStdExtM, 245 FeatureStdExtA, 246 FeatureStdExtC]>; 247 248def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit, 249 FeatureStdExtM, 250 FeatureStdExtA, 251 FeatureStdExtF, 252 FeatureStdExtD, 253 FeatureStdExtC]>; 254 255def : ProcessorModel<"sifive-e76", SiFive7Model, [FeatureStdExtM, 256 FeatureStdExtA, 257 FeatureStdExtF, 258 FeatureStdExtC]>; 259 260def : ProcessorModel<"sifive-u74", SiFive7Model, [Feature64Bit, 261 FeatureStdExtM, 262 FeatureStdExtA, 263 FeatureStdExtF, 264 FeatureStdExtD, 265 FeatureStdExtC]>; 266 267//===----------------------------------------------------------------------===// 268// Define the RISC-V target. 269//===----------------------------------------------------------------------===// 270 271def RISCVInstrInfo : InstrInfo { 272 let guessInstructionProperties = 0; 273} 274 275def RISCVAsmParser : AsmParser { 276 let ShouldEmitMatchRegisterAltName = 1; 277 let AllowDuplicateRegisterNames = 1; 278} 279 280def RISCVAsmWriter : AsmWriter { 281 int PassSubtarget = 1; 282} 283 284def RISCV : Target { 285 let InstructionSet = RISCVInstrInfo; 286 let AssemblyParsers = [RISCVAsmParser]; 287 let AssemblyWriters = [RISCVAsmWriter]; 288 let AllowRegisterRenaming = 1; 289} 290