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Searched refs:DstReg (Results 1 – 25 of 332) sorted by relevance

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/external/mesa3d/src/mesa/program/
Dprogramopt.c90 newInst[i].DstReg.File = PROGRAM_OUTPUT; in insert_mvp_dp4_code()
91 newInst[i].DstReg.Index = VARYING_SLOT_POS; in insert_mvp_dp4_code()
92 newInst[i].DstReg.WriteMask = (WRITEMASK_X << i); in insert_mvp_dp4_code()
161 newInst[0].DstReg.File = PROGRAM_TEMPORARY; in insert_mvp_mad_code()
162 newInst[0].DstReg.Index = hposTemp; in insert_mvp_mad_code()
163 newInst[0].DstReg.WriteMask = WRITEMASK_XYZW; in insert_mvp_mad_code()
173 newInst[i].DstReg.File = PROGRAM_TEMPORARY; in insert_mvp_mad_code()
174 newInst[i].DstReg.Index = hposTemp; in insert_mvp_mad_code()
175 newInst[i].DstReg.WriteMask = WRITEMASK_XYZW; in insert_mvp_mad_code()
188 newInst[3].DstReg.File = PROGRAM_OUTPUT; in insert_mvp_mad_code()
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Dprog_optimize.c79 channel_mask = inst->DstReg.WriteMask & dst_mask; in get_src_arg_mask()
123 const GLuint mask = mov->DstReg.WriteMask; in get_dst_mask_for_mov()
224 if (inst->DstReg.File == file) { in replace_regs()
225 const GLuint index = inst->DstReg.Index; in replace_regs()
227 inst->DstReg.Index = map[index]; in replace_regs()
288 if (inst->DstReg.File == PROGRAM_TEMPORARY) { in _mesa_remove_dead_code_global()
289 assert(inst->DstReg.Index < REG_ALLOCATE_MAX_PROGRAM_TEMPS); in _mesa_remove_dead_code_global()
291 if (inst->DstReg.RelAddr) { in _mesa_remove_dead_code_global()
304 if (numDst != 0 && inst->DstReg.File == PROGRAM_TEMPORARY) { in _mesa_remove_dead_code_global()
305 GLint chan, index = inst->DstReg.Index; in _mesa_remove_dead_code_global()
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Dprog_instruction.c55 inst[i].DstReg.File = PROGRAM_UNDEFINED; in _mesa_init_instructions()
56 inst[i].DstReg.WriteMask = WRITEMASK_XYZW; in _mesa_init_instructions()
212 if (inst->DstReg.WriteMask == WRITEMASK_X || in _mesa_check_soa_dependencies()
213 inst->DstReg.WriteMask == WRITEMASK_Y || in _mesa_check_soa_dependencies()
214 inst->DstReg.WriteMask == WRITEMASK_Z || in _mesa_check_soa_dependencies()
215 inst->DstReg.WriteMask == WRITEMASK_W || in _mesa_check_soa_dependencies()
216 inst->DstReg.WriteMask == 0x0) { in _mesa_check_soa_dependencies()
223 if (inst->SrcReg[i].File == inst->DstReg.File && in _mesa_check_soa_dependencies()
224 inst->SrcReg[i].Index == inst->DstReg.Index) { in _mesa_check_soa_dependencies()
228 if (inst->DstReg.WriteMask & (1 << chan)) { in _mesa_check_soa_dependencies()
/external/mesa3d/src/gallium/drivers/r300/compiler/
Dradeon_program_tex.c68 inst_mov->U.I.DstReg.File = RC_FILE_TEMPORARY; in scale_texcoords()
69 inst_mov->U.I.DstReg.Index = temp; in scale_texcoords()
90 inst_rcp->U.I.DstReg.File = RC_FILE_TEMPORARY; in projective_divide()
91 inst_rcp->U.I.DstReg.Index = temp; in projective_divide()
92 inst_rcp->U.I.DstReg.WriteMask = RC_MASK_W; in projective_divide()
101 inst_mul->U.I.DstReg.File = RC_FILE_TEMPORARY; in projective_divide()
102 inst_mul->U.I.DstReg.Index = temp; in projective_divide()
165 struct rc_dst_register output_reg = inst->U.I.DstReg; in radeonTransformTEX()
171 inst->U.I.DstReg.File = RC_FILE_TEMPORARY; in radeonTransformTEX()
172 inst->U.I.DstReg.Index = tmp_texsample; in radeonTransformTEX()
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Dradeon_program_alu.c45 struct rc_dst_register DstReg, struct rc_src_register SrcReg) in emit1() argument
54 fpi->U.I.DstReg = DstReg; in emit1()
62 struct rc_dst_register DstReg, in emit2() argument
72 fpi->U.I.DstReg = DstReg; in emit2()
81 struct rc_dst_register DstReg, in emit3() argument
92 fpi->U.I.DstReg = DstReg; in emit3()
204 if (inst->U.I.DstReg.File != RC_FILE_TEMPORARY) in is_dst_safe_to_reuse()
209 inst->U.I.SrcReg[i].Index == inst->U.I.DstReg.Index) in is_dst_safe_to_reuse()
222 tmp = inst->U.I.DstReg.Index; in try_to_reuse_dst()
226 return dstregtmpmask(tmp, inst->U.I.DstReg.WriteMask); in try_to_reuse_dst()
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Dr3xx_vertprog.c194 t_dst_index(vp, &vpi->DstReg), in ei_vector1()
195 t_dst_mask(vpi->DstReg.WriteMask), in ei_vector1()
196 t_dst_class(vpi->DstReg.File), in ei_vector1()
211 t_dst_index(vp, &vpi->DstReg), in ei_vector2()
212 t_dst_mask(vpi->DstReg.WriteMask), in ei_vector2()
213 t_dst_class(vpi->DstReg.File), in ei_vector2()
228 t_dst_index(vp, &vpi->DstReg), in ei_math1()
229 t_dst_mask(vpi->DstReg.WriteMask), in ei_math1()
230 t_dst_class(vpi->DstReg.File), in ei_math1()
246 t_dst_index(vp, &vpi->DstReg), in ei_lit()
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Dradeon_compiler.c130 if (inst->U.I.DstReg.File == RC_FILE_OUTPUT) in rc_calculate_inputs_outputs()
131 c->Program.OutputsWritten |= 1 << inst->U.I.DstReg.Index; in rc_calculate_inputs_outputs()
182 if (inst->U.I.DstReg.File == RC_FILE_OUTPUT && inst->U.I.DstReg.Index == output) { in rc_move_output()
183 inst->U.I.DstReg.Index = new_output; in rc_move_output()
184 inst->U.I.DstReg.WriteMask &= writemask; in rc_move_output()
205 if (inst->U.I.DstReg.File == RC_FILE_OUTPUT && inst->U.I.DstReg.Index == output) { in rc_copy_output()
206 inst->U.I.DstReg.File = RC_FILE_TEMPORARY; in rc_copy_output()
207 inst->U.I.DstReg.Index = tempreg; in rc_copy_output()
214 inst->U.I.DstReg.File = RC_FILE_OUTPUT; in rc_copy_output()
215 inst->U.I.DstReg.Index = output; in rc_copy_output()
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Dradeon_emulate_branches.c76 inst_mov->U.I.DstReg.File = RC_FILE_TEMPORARY; in handle_if()
77 inst_mov->U.I.DstReg.Index = rc_find_free_temporary(s->C); in handle_if()
78 inst_mov->U.I.DstReg.WriteMask = RC_MASK_X; in handle_if()
82 inst->U.I.SrcReg[0].Index = inst_mov->U.I.DstReg.Index; in handle_if()
166 inst_mov->U.I.DstReg.File = RC_FILE_TEMPORARY; in allocate_and_insert_proxies()
167 inst_mov->U.I.DstReg.Index = proxies->Temporary[index].Index; in allocate_and_insert_proxies()
168 inst_mov->U.I.DstReg.WriteMask = RC_MASK_XYZW; in allocate_and_insert_proxies()
185 inst_cmp->U.I.DstReg.File = file; in inject_cmp()
186 inst_cmp->U.I.DstReg.Index = index; in inject_cmp()
187 inst_cmp->U.I.DstReg.WriteMask = RC_MASK_XYZW; in inject_cmp()
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Dradeon_pair_translate.c90 *needrgb = (inst->DstReg.WriteMask & RC_MASK_XYZ) ? 1 : 0; in classify_instruction()
91 *needalpha = (inst->DstReg.WriteMask & RC_MASK_W) ? 1 : 0; in classify_instruction()
275 inst->DstReg.WriteMask); in set_pair_instruction()
284 if (inst->DstReg.File == RC_FILE_OUTPUT) { in set_pair_instruction()
285 if (inst->DstReg.Index == c->OutputDepth) { in set_pair_instruction()
286 pair->Alpha.DepthWriteMask |= GET_BIT(inst->DstReg.WriteMask, 3); in set_pair_instruction()
289 if (inst->DstReg.Index == c->OutputColor[i]) { in set_pair_instruction()
293 inst->DstReg.WriteMask & RC_MASK_XYZ; in set_pair_instruction()
295 GET_BIT(inst->DstReg.WriteMask, 3); in set_pair_instruction()
302 pair->RGB.DestIndex = inst->DstReg.Index; in set_pair_instruction()
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/external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
DLegalizationArtifactCombiner.h54 Register DstReg = MI.getOperand(0).getReg(); in tryCombineAnyExt() local
61 Builder.buildAnyExtOrTrunc(DstReg, TruncSrc); in tryCombineAnyExt()
62 UpdatedDefs.push_back(DstReg); in tryCombineAnyExt()
74 Builder.buildInstr(ExtMI->getOpcode(), {DstReg}, {ExtSrc}); in tryCombineAnyExt()
75 UpdatedDefs.push_back(DstReg); in tryCombineAnyExt()
84 const LLT DstTy = MRI.getType(DstReg); in tryCombineAnyExt()
88 DstReg, CstVal.getCImm()->getValue().sext(DstTy.getSizeInBits())); in tryCombineAnyExt()
89 UpdatedDefs.push_back(DstReg); in tryCombineAnyExt()
104 Register DstReg = MI.getOperand(0).getReg(); in tryCombineZExt() local
113 LLT DstTy = MRI.getType(DstReg); in tryCombineZExt()
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/external/llvm/lib/Target/AMDGPU/
DR600ExpandSpecialInstrs.cpp126 unsigned DstReg; in runOnMachineFunction() local
129 DstReg = MI.getOperand(Chan).getReg(); in runOnMachineFunction()
131 DstReg = Chan == 2 ? AMDGPU::T0_Z : AMDGPU::T0_W; in runOnMachineFunction()
134 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg); in runOnMachineFunction()
155 unsigned DstReg; in runOnMachineFunction() local
158 DstReg = Chan == 0 ? AMDGPU::T0_X : AMDGPU::T0_Y; in runOnMachineFunction()
160 DstReg = MI.getOperand(Chan-2).getReg(); in runOnMachineFunction()
163 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg); in runOnMachineFunction()
183 unsigned DstReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
187 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg); in runOnMachineFunction()
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/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DLegalizationArtifactCombiner.h54 Register DstReg = MI.getOperand(0).getReg(); in tryCombineAnyExt() local
61 Builder.buildAnyExtOrTrunc(DstReg, TruncSrc); in tryCombineAnyExt()
62 UpdatedDefs.push_back(DstReg); in tryCombineAnyExt()
74 Builder.buildInstr(ExtMI->getOpcode(), {DstReg}, {ExtSrc}); in tryCombineAnyExt()
75 UpdatedDefs.push_back(DstReg); in tryCombineAnyExt()
84 const LLT &DstTy = MRI.getType(DstReg); in tryCombineAnyExt()
88 DstReg, CstVal.getCImm()->getValue().sext(DstTy.getSizeInBits())); in tryCombineAnyExt()
89 UpdatedDefs.push_back(DstReg); in tryCombineAnyExt()
103 Register DstReg = MI.getOperand(0).getReg(); in tryCombineZExt() local
109 LLT DstTy = MRI.getType(DstReg); in tryCombineZExt()
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/external/llvm-project/llvm/lib/Target/AVR/
DAVRExpandPseudoInsts.cpp69 Register DstReg) { in buildMI() argument
70 return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode), DstReg); in buildMI()
145 Register DstReg = MI.getOperand(0).getReg(); in expandArith() local
152 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandArith()
178 Register DstReg = MI.getOperand(0).getReg(); in expandLogic() local
185 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandLogic()
225 Register DstReg = MI.getOperand(0).getReg(); in expandLogicImm() local
232 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandLogicImm()
277 Register DstReg = MI.getOperand(0).getReg(); in expand() local
281 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRExpandPseudoInsts.cpp69 unsigned DstReg) { in buildMI() argument
70 return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode), DstReg); in buildMI()
145 Register DstReg = MI.getOperand(0).getReg(); in expandArith() local
152 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandArith()
178 Register DstReg = MI.getOperand(0).getReg(); in expandLogic() local
185 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandLogic()
225 Register DstReg = MI.getOperand(0).getReg(); in expandLogicImm() local
232 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandLogicImm()
277 unsigned DstReg = MI.getOperand(0).getReg(); in expand() local
281 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp191 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
202 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
206 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) { in getDuplexCandidateGroup()
220 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
222 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && in getDuplexCandidateGroup()
241 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
243 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && in getDuplexCandidateGroup()
251 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
253 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && in getDuplexCandidateGroup()
261 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
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/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp178 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
189 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
193 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) { in getDuplexCandidateGroup()
207 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
209 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && in getDuplexCandidateGroup()
228 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
230 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && in getDuplexCandidateGroup()
238 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
240 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && in getDuplexCandidateGroup()
248 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
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/external/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp190 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
201 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
205 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) { in getDuplexCandidateGroup()
219 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
221 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && in getDuplexCandidateGroup()
240 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
242 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && in getDuplexCandidateGroup()
250 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
252 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && in getDuplexCandidateGroup()
260 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
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/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonPeephole.cpp139 Register DstReg = Dst.getReg(); in runOnMachineFunction() local
142 if (DstReg.isVirtual() && SrcReg.isVirtual()) { in runOnMachineFunction()
146 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
159 Register DstReg = Dst.getReg(); in runOnMachineFunction() local
161 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
176 Register DstReg = Dst.getReg(); in runOnMachineFunction() local
178 PeepholeDoubleRegsMap[DstReg] = in runOnMachineFunction()
187 Register DstReg = Dst.getReg(); in runOnMachineFunction() local
190 if (DstReg.isVirtual() && SrcReg.isVirtual()) { in runOnMachineFunction()
194 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonPeephole.cpp139 Register DstReg = Dst.getReg(); in runOnMachineFunction() local
142 if (Register::isVirtualRegister(DstReg) && in runOnMachineFunction()
147 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
160 Register DstReg = Dst.getReg(); in runOnMachineFunction() local
162 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
177 Register DstReg = Dst.getReg(); in runOnMachineFunction() local
179 PeepholeDoubleRegsMap[DstReg] = in runOnMachineFunction()
188 Register DstReg = Dst.getReg(); in runOnMachineFunction() local
191 if (Register::isVirtualRegister(DstReg) && in runOnMachineFunction()
196 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
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/external/llvm-project/llvm/lib/Target/X86/
DX86InstructionSelector.cpp109 const unsigned DstReg,
122 bool emitInsertSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I,
125 bool emitExtractSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I,
234 Register DstReg = I.getOperand(0).getReg(); in selectCopy() local
235 const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI); in selectCopy()
236 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
242 if (DstReg.isPhysical()) { in selectCopy()
250 const TargetRegisterClass *DstRC = getRegClassFromGRPhysReg(DstReg); in selectCopy()
279 getRegClass(MRI.getType(DstReg), DstRegBank); in selectCopy()
297 const TargetRegisterClass *OldRC = MRI.getRegClassOrNull(DstReg); in selectCopy()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstructionSelector.cpp108 const unsigned DstReg,
121 bool emitInsertSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I,
124 bool emitExtractSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I,
233 Register DstReg = I.getOperand(0).getReg(); in selectCopy() local
234 const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI); in selectCopy()
235 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
241 if (Register::isPhysicalRegister(DstReg)) { in selectCopy()
249 const TargetRegisterClass *DstRC = getRegClassFromGRPhysReg(DstReg); in selectCopy()
278 getRegClass(MRI.getType(DstReg), DstRegBank); in selectCopy()
296 const TargetRegisterClass *OldRC = MRI.getRegClassOrNull(DstReg); in selectCopy()
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/external/llvm-project/llvm/lib/Target/AMDGPU/
DSILowerI1Copies.cpp95 unsigned DstReg, unsigned PrevReg, unsigned CurReg);
514 Register DstReg = MI.getOperand(0).getReg(); in lowerCopiesFromI1() local
519 if (isLaneMaskReg(DstReg) || isVreg1(DstReg)) in lowerCopiesFromI1()
526 assert(isVRegCompatibleReg(TII->getRegisterInfo(), *MRI, DstReg)); in lowerCopiesFromI1()
530 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstReg) in lowerCopiesFromI1()
574 Register DstReg = MI->getOperand(0).getReg(); in lowerPhis() local
575 MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass in lowerPhis()
600 PhiRegisters.insert(DstReg); in lowerPhis()
606 for (MachineInstr &Use : MRI->use_instructions(DstReg)) in lowerPhis()
613 SSAUpdater.Initialize(DstReg); in lowerPhis()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSILowerI1Copies.cpp95 unsigned DstReg, unsigned PrevReg, unsigned CurReg);
510 Register DstReg = MI.getOperand(0).getReg(); in lowerCopiesFromI1() local
515 if (isLaneMaskReg(DstReg) || isVreg1(DstReg)) in lowerCopiesFromI1()
522 assert(isVRegCompatibleReg(TII->getRegisterInfo(), *MRI, DstReg)); in lowerCopiesFromI1()
526 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstReg) in lowerCopiesFromI1()
570 Register DstReg = MI->getOperand(0).getReg(); in lowerPhis() local
571 MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass in lowerPhis()
596 PhiRegisters.insert(DstReg); in lowerPhis()
602 for (MachineInstr &Use : MRI->use_instructions(DstReg)) in lowerPhis()
609 SSAUpdater.Initialize(DstReg); in lowerPhis()
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/external/llvm/lib/Target/Hexagon/
DHexagonPeephole.cpp142 unsigned DstReg = Dst.getReg(); in runOnMachineFunction() local
145 if (TargetRegisterInfo::isVirtualRegister(DstReg) && in runOnMachineFunction()
150 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
163 unsigned DstReg = Dst.getReg(); in runOnMachineFunction() local
165 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
180 unsigned DstReg = Dst.getReg(); in runOnMachineFunction() local
182 PeepholeDoubleRegsMap[DstReg] = in runOnMachineFunction()
191 unsigned DstReg = Dst.getReg(); in runOnMachineFunction() local
194 if (TargetRegisterInfo::isVirtualRegister(DstReg) && in runOnMachineFunction()
199 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
DBPFMISimplifyPatchable.cpp57 MachineInstr &MI, Register &SrcReg, Register &DstReg,
59 void processDstReg(MachineRegisterInfo *MRI, Register &DstReg,
147 Register &DstReg, const GlobalValue *GVal) { in processCandidate() argument
148 if (MRI->getRegClass(DstReg) == &BPF::GPR32RegClass) { in processCandidate()
155 auto Begin = MRI->use_begin(DstReg), End = MRI->use_end(); in processCandidate()
165 processDstReg(MRI, TmpReg, DstReg, GVal, false); in processCandidate()
169 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::COPY), DstReg) in processCandidate()
175 processDstReg(MRI, DstReg, SrcReg, GVal, true); in processCandidate()
179 Register &DstReg, Register &SrcReg, const GlobalValue *GVal, in processDstReg() argument
181 auto Begin = MRI->use_begin(DstReg), End = MRI->use_end(); in processDstReg()
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