Searched refs:EL1 (Results 1 – 25 of 60) sorted by relevance
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11 the interrupt to either software in EL3 or Secure-EL1 depending upon the21 knowledge of software executing in Secure-EL1/Secure-EL0. The choice of35 #. Secure EL1 interrupt. This type of interrupt can be routed to EL3 or36 Secure-EL1 depending upon the security state of the current execution37 context. It is always handled in Secure-EL1.40 Secure-EL1, Non-secure EL1 or EL2 depending upon the security state of the41 current execution context. It is always handled in either Non-secure EL144 #. EL3 interrupt. This type of interrupt can be routed to EL3 or Secure-EL185 for GIC version 3.0 (Arm GICv3) and only the Secure-EL1 and Non-secure interrupt95 Secure-EL1 interrupts[all …]
49 - Boot Loader stage 3-2 (BL32) *Secure-EL1 Payload* (optional)212 SYS_LED[2:1] - Exception Level (EL3=0x3, EL2=0x2, EL1=0x1, EL0=0x0)252 - ``CPTR_EL3``. Accesses to the ``CPACR_EL1`` register from EL1 or EL2, or the267 disable AArch32 Secure self-hosted privileged debug from S-EL1.356 #. BL1 passes control to the BL2 image at Secure EL1 (for AArch64) or at362 BL1 loads and passes control to BL2 at Secure-EL1 (for AArch64) or at Secure371 for subsequent stages of TF-A and normal world software. EL1 and EL0 are given428 AArch64 BL32 (Secure-EL1 Payload) image load437 Secure-EL1 Payload Dispatcher (see later) within BL31, which is responsible for474 as its only purpose is to ensure TF-A BL2 is entered at S-EL1. To avoid[all …]
5 | Title | RO memory is always executable at AArch64 Secure EL1 |15 | Affected | executing at AArch64 Secure EL1 |34 This feature does not work correctly for AArch64 images executing at Secure EL1.58 determine whether a region is executable. The Secure EL1&0 translation regime61 in the Secure EL1&0 regime. As a result, this programs the Secure EL0 execution62 permissions but always leaves the memory as executable at Secure EL1.
43 meaning that debug exceptions from Secure EL1 are enabled by the authentication44 interface. Therefore this issue only exists for AArch32 Secure EL1 code when50 from AArch32 Secure EL1.
53 Secure-EL1 and executing the ``BPIALL`` instruction. This workaround is75 disable/enable" and "BPIALL at AArch32 Secure-EL1" workarounds described above.80 at invalidating the branch predictor on Cortex-A57, the drop into Secure-EL197 | ``PSCI_VERSION`` with "BPIALL at AArch32 Secure-EL1" | 1276 |99 | ``SMCCC_ARCH_WORKAROUND_1`` with "BPIALL at AArch32 Secure-EL1" | 770 |131 translation regime, for example between EL0 and EL1, therefore this variant
39 transitioning to S-EL1.50 NOTE: The original pull request referenced above only fixed the issue for S-EL1
65 ; CHECK: [[EL1:%[a-zA-Z0-9_]+]] = extractelement <4 x float> [[VEC4]], i32 066 ; CHECK: store float [[EL1]]
30 … 0x00 0x00 0x00 0x00 0x00 0x00 ]; I_CTXT : Context Packet.; Ctxt: AArch32, EL1, NS; CID=0x00000000…36 … 0x00 0x00 0x00 0x00 0x00 0x00 ]; I_CTXT : Context Packet.; Ctxt: AArch32, EL1, NS; CID=0x00000000…
43 privileged Exception Level (i.e. EL3 or S-EL1) makes security auditing of127 Payload image executing at S-EL1 (e.g. a Trusted OS). Both are referred to as265 A SVC causes an exception to be taken to S-EL1. TF-A assumes ownership of S-EL1266 and installs a simple exception vector table in S-EL1 that relays a SVC request301 the Secure EL1&0 translation regime).410 description and initialises the Secure EL1&0 translation regime as follows.429 S-EL0 or S-EL1.491 buffer will be mapped in the Secure EL1&0 translation regime with read-only563 The buffer is mapped in the Secure EL1&0 translation regime with read-only609 the Secure EL1&0 Translation regime with appropriate memory attributes.[all …]
69 resides at EL3 and S-EL2 (or EL3 and S-EL1).83 - Alternatively, SPMC can refer to an S-EL1 component, itself being a Secure94 kernel) to SPMC located either at S-EL1 or S-EL2.98 - S-EL1 supporting pre-Armv8.4 platforms. SPMD conveys FF-A protocol99 from EL3 to S-EL1.123 level to being S-EL1 or S-EL2. It defaults to enabled (value 1) when139 | SPMC at S-EL1 (e.g. OP-TEE) | 0 | 0 |163 Sample TF-A build command line when SPMC is located at S-EL1314 setup a SP that co-resides with the SPMC and executes at S-EL1 or Secure337 Hafnium, or AArch64/AArch32 for OP-TEE at S-EL1).[all …]
153 Secure EL1 interrupts.156 for Secure EL1 interrupts.173 - ``INTR_TYPE_S_EL1``: interrupt is meant to be consumed by Secure EL1.
147 - On GICv3 systems, when executing in S-EL1, pending Non-secure interrupts of149 EL3. As a result, S-EL1 software cannot expect to handle Non-secure150 interrupts at S-EL1. Essentially, this deprecates the routing mode described153 In order for S-EL1 software to handle Non-secure interrupts while having156 handled over to S-EL1.489 to be taken to S-EL1 [#irq]_, so would get a chance to populate the designated500 .. [#irq] In case of GICv2, Non-secure interrupts while in S-EL1 were signalled
74 the EL1&0 translation regime, the attributes also specify whether the region is75 a User region (EL0) or Privileged region (EL1). See the ``MT_xxx`` definitions76 in ``xlat_tables_v2.h``. Note that for the EL1&0 translation regime the Execute77 Never attribute is set simultaneously for both EL1 and EL0.111 create translation tables pertaining to the S-EL1&0 translation regime.
4 `OP-TEE OS`_ is a Trusted OS running as Secure EL1.
20 TLK is a Trusted OS running as Secure EL1. It is a Free Open Source Software
282 The PSCI and Test Secure-EL1 Payload Dispatcher services do not follow302 Secure-EL1 Payload Dispatcher service (SPD)306 or other Secure-EL1 Payload are special. These services need to manage the307 Secure-EL1 context, provide the *Secure Monitor* functionality of switching308 between the normal and secure worlds, deliver SMC Calls through to Secure-EL1309 and generally manage the Secure-EL1 Payload through CPU power-state transitions.
65 Secure-EL1 Payload (SP): ``AP_BL32``69 normal world. However, it may refer to a more abstract Secure-EL1 Payload (SP).71 single or primary image executing at Secure-EL1. In systems where there are
22 exception-level = <2>; /* S-EL1 */
79 - If set to ``0``, will increment the associated ``PMEVCNTR<n>`` at EL1.85 Non-secure EL1.
23 ; CHECK: @static_struct.1 = internal unnamed_addr global i64 0, align 8, !dbg ![[EL1:.*]]27 ; CHECK: ![[EL1]] = !DIGlobalVariableExpression(var: ![[VAR]], expr: !DIExpression(DW_OP_LLVM_fragm…
25 ; CHECK: @array.1.0 = internal unnamed_addr global i32 0, align 8, !dbg ![[EL1:.*]]29 ; CHECK: ![[EL1]] = !DIGlobalVariableExpression(var: ![[VAR]], expr: !DIExpression(DW_OP_LLVM_fragm…
25 …array.1 = internal unnamed_addr global x86_fp80 0xK00000000000000000000, align 16, !dbg ![[EL1:.*]]29 ; CHECK: ![[EL1]] = !DIGlobalVariableExpression(var: ![[VAR]], expr: !DIExpression(DW_OP_LLVM_fragm…
28 ; CHECK: @static_struct.1 = internal unnamed_addr global i32 0, align 16, !dbg ![[EL1:.*]]32 ; CHECK: ![[EL1]] = !DIGlobalVariableExpression(var: ![[VAR]], expr: !DIExpression(DW_OP_LLVM_fragm…
40 - Secure Monitor library code such as world switching, EL1 context management42 When a Secure-EL1 Payload (SP) is present, for example a Secure OS, the
92 enum ExceptionLevel { EL0 = 0, EL1 = 1, EL2 = 2, EL3 = 3 }; enumerator