Searched refs:EL1_EL0_REGIME (Results 1 – 8 of 8) sorted by relevance
102 tf_xlat_ctx.xlat_regime = EL1_EL0_REGIME; in init_xlat_tables()144 if (tf_xlat_ctx.xlat_regime == EL1_EL0_REGIME) { in xlat_make_tables_readonly()156 assert(tf_xlat_ctx.xlat_regime == EL1_EL0_REGIME); in xlat_make_tables_readonly()174 if (tf_xlat_ctx.xlat_regime == EL1_EL0_REGIME) { in xlat_make_tables_readonly()215 tf_xlat_ctx.va_max_address, EL1_EL0_REGIME); in enable_mmu_el1()258 tf_xlat_ctx.va_max_address, EL1_EL0_REGIME); in enable_mmu_svc_mon()
71 assert(xlat_regime == EL1_EL0_REGIME); in xlat_desc_print()82 uint64_t xn_mask = xlat_arch_regime_get_xn_desc(EL1_EL0_REGIME); in xlat_desc_print()210 if (ctx->xlat_regime == EL1_EL0_REGIME) { in xlat_tables_print()342 assert((ctx->xlat_regime == EL1_EL0_REGIME) || in xlat_get_mem_attributes_internal()398 if (ctx->xlat_regime == EL1_EL0_REGIME) { in xlat_get_mem_attributes_internal()
140 if (ctx->xlat_regime == EL1_EL0_REGIME) { in xlat_desc()1191 (ctx->xlat_regime == EL1_EL0_REGIME)); in init_xlat_tables_ctx()
60 if (ctx->xlat_regime == EL1_EL0_REGIME) { in is_mmu_enabled_ctx()81 if (xlat_regime == EL1_EL0_REGIME) { in xlat_arch_regime_get_xn_desc()97 if (xlat_regime == EL1_EL0_REGIME) { in xlat_arch_tlbi_va()176 if (xlat_regime == EL1_EL0_REGIME) { in setup_mmu_cfg()
123 if (ctx->xlat_regime == EL1_EL0_REGIME) { in is_mmu_enabled_ctx()151 if (xlat_regime == EL1_EL0_REGIME) { in xlat_arch_regime_get_xn_desc()175 if (xlat_regime == EL1_EL0_REGIME) { in xlat_arch_tlbi_va()273 if (xlat_regime == EL1_EL0_REGIME) { in setup_mmu_cfg()
33 EL1_EL0_REGIME, PLAT_SP_IMAGE_XLAT_SECTION_NAME,
117 EL1_EL0_REGIME); in spm_sp_setup()
147 #define EL1_EL0_REGIME 1 macro