| /external/llvm-project/llvm/test/TableGen/ |
| D | dag-isel-subregs.td | 5 // CHECK-LABEL: OPC_CheckOpcode, TARGET_VAL(ISD::EXTRACT_SUBVECTOR),
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| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | extract-subvector-equal-length.ll | 4 ; Test for ICE in SelectionDAG::computeKnownBits when visiting EXTRACT_SUBVECTOR
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| /external/llvm-project/llvm/test/Transforms/InstCombine/ |
| D | canonicalize-vector-extract.ll | 5 ; scalable case, we lower to the EXTRACT_SUBVECTOR ISD node.
131 ; EXTRACT_SUBVECTOR ISD node later.
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 338 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom); in AMDGPUTargetLowering()
339 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom); in AMDGPUTargetLowering()
340 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3f32, Custom); in AMDGPUTargetLowering()
341 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3i32, Custom); in AMDGPUTargetLowering()
342 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom); in AMDGPUTargetLowering()
343 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom); in AMDGPUTargetLowering()
344 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5f32, Custom); in AMDGPUTargetLowering()
345 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5i32, Custom); in AMDGPUTargetLowering()
346 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom); in AMDGPUTargetLowering()
347 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom); in AMDGPUTargetLowering()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 53 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; in ScalarizeVectorResult()
833 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break; in SplitVectorResult()
1117 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx); in SplitVecRes_EXTRACT_SUBVECTOR()
1119 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, in SplitVecRes_EXTRACT_SUBVECTOR()
1927 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break; in SplitVectorOperand()
2160 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx); in SplitVecOp_EXTRACT_SUBVECTOR()
2162 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi, in SplitVecOp_EXTRACT_SUBVECTOR()
2691 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break; in WidenVectorResult()
3012 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1, in WidenVecRes_BinaryCanTrap()
3015 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2, in WidenVecRes_BinaryCanTrap()
[all …]
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| D | DAGCombiner.cpp | 1602 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); in visit()
10995 if (!LegalTypes && N0.getOpcode() == ISD::EXTRACT_SUBVECTOR) { in visitTRUNCATE()
11002 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N0->getOperand(0)), VT, in visitTRUNCATE()
15425 Val.getOpcode() == ISD::EXTRACT_SUBVECTOR)) { in MergeStoresOfConstantsOrVecElts()
15431 unsigned OpC = MemVT.isVector() ? ISD::EXTRACT_SUBVECTOR in MergeStoresOfConstantsOrVecElts()
15535 Val.getOpcode() == ISD::EXTRACT_SUBVECTOR); in getStoreMergeCandidates()
15605 OtherBC.getOpcode() != ISD::EXTRACT_SUBVECTOR) in getStoreMergeCandidates()
15767 StoredVal.getOpcode() == ISD::EXTRACT_SUBVECTOR); in MergeConsecutiveStores()
17467 VecIn2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, VecIn1, in createBuildVecShuffle()
17469 VecIn1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, VecIn1, ZeroIdx); in createBuildVecShuffle()
[all …]
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 54 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; in ScalarizeVectorResult()
889 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break; in SplitVectorResult()
1215 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx); in SplitVecRes_EXTRACT_SUBVECTOR()
1218 ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, in SplitVecRes_EXTRACT_SUBVECTOR()
2064 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break; in SplitVectorOperand()
2302 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx); in SplitVecOp_EXTRACT_SUBVECTOR()
2304 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi, in SplitVecOp_EXTRACT_SUBVECTOR()
2845 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break; in WidenVectorResult()
3172 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1, in WidenVecRes_BinaryCanTrap()
3174 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2, in WidenVecRes_BinaryCanTrap()
[all …]
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| D | DAGCombiner.cpp | 655 case ISD::EXTRACT_SUBVECTOR: in getStoreSource()
1724 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); in visit()
11982 if (!LegalTypes && N0.getOpcode() == ISD::EXTRACT_SUBVECTOR) { in visitTRUNCATE()
11989 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N0->getOperand(0)), VT, in visitTRUNCATE()
16468 Val.getOpcode() == ISD::EXTRACT_SUBVECTOR)) { in mergeStoresOfConstantsOrVecElts()
16474 unsigned OpC = MemVT.isVector() ? ISD::EXTRACT_SUBVECTOR in mergeStoresOfConstantsOrVecElts()
16642 OtherBC.getOpcode() != ISD::EXTRACT_SUBVECTOR) in getStoreMergeCandidates()
18732 VecIn2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, VecIn1, in createBuildVecShuffle()
18734 VecIn1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, VecIn1, ZeroIdx); in createBuildVecShuffle()
18804 Shuffle = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Shuffle, ZeroIdx); in createBuildVecShuffle()
[all …]
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 299 EXTRACT_SUBVECTOR, enumerator
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 55 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; in ScalarizeVectorResult()
597 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break; in SplitVectorResult()
838 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx); in SplitVecRes_EXTRACT_SUBVECTOR()
840 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, in SplitVecRes_EXTRACT_SUBVECTOR()
1461 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break; in SplitVectorOperand()
1607 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx); in SplitVecOp_EXTRACT_SUBVECTOR()
1609 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi, in SplitVecOp_EXTRACT_SUBVECTOR()
2062 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break; in WidenVectorResult()
2243 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1, in WidenVecRes_BinaryCanTrap()
2246 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2, in WidenVecRes_BinaryCanTrap()
[all …]
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| D | SelectionDAGDumper.cpp | 222 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; in getOperationName()
|
| /external/llvm-project/llvm/unittests/CodeGen/ |
| D | AArch64SelectionDAGTest.cpp | 130 auto Op = DAG->getNode(ISD::EXTRACT_SUBVECTOR, Loc, VecVT, Vec, ZeroIdx); in TEST_F()
173 auto Op = DAG->getNode(ISD::EXTRACT_SUBVECTOR, Loc, VecVT, Vec, ZeroIdx); in TEST_F()
190 auto Op = DAG->getNode(ISD::EXTRACT_SUBVECTOR, Loc, VecVT, Vec, ZeroIdx); in TEST_F()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 412 EXTRACT_SUBVECTOR, enumerator
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 541 EXTRACT_SUBVECTOR, enumerator
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 286 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom); in AMDGPUTargetLowering()
287 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom); in AMDGPUTargetLowering()
288 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3f32, Custom); in AMDGPUTargetLowering()
289 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3i32, Custom); in AMDGPUTargetLowering()
290 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom); in AMDGPUTargetLowering()
291 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom); in AMDGPUTargetLowering()
292 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5f32, Custom); in AMDGPUTargetLowering()
293 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5i32, Custom); in AMDGPUTargetLowering()
294 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom); in AMDGPUTargetLowering()
295 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom); in AMDGPUTargetLowering()
[all …]
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| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | sve-fixed-length-subvector.ll | 22 ; fixed_length_vector = ISD::EXTRACT_SUBVECTOR scalable_vector, 0
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 269 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom); in AMDGPUTargetLowering()
270 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom); in AMDGPUTargetLowering()
271 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom); in AMDGPUTargetLowering()
272 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom); in AMDGPUTargetLowering()
273 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom); in AMDGPUTargetLowering()
274 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom); in AMDGPUTargetLowering()
708 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); in LowerOperation()
|
| /external/llvm-project/llvm/test/CodeGen/X86/ |
| D | vec_extract-avx.ll | 7 ; an EXTRACT_SUBVECTOR node internally rather than a bunch of
|
| /external/llvm/test/CodeGen/X86/ |
| D | vec_extract-avx.ll | 7 ; an EXTRACT_SUBVECTOR node internally rather than a bunch of
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 669 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in addTypeForNEON()
2373 case ISD::EXTRACT_SUBVECTOR: in LowerOperation()
5035 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
5041 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
5046 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
5049 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
5389 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0, in tryFormConcatFromShuffle()
5393 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1, in tryFormConcatFromShuffle()
5615 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) { in LowerVECTOR_SHUFFLE()
8001 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR && in performBitcastCombine()
[all …]
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 1099 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
1262 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in addTypeForNEON()
1322 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in addTypeForFixedLengthSVE()
4056 DAG.getNode(ISD::EXTRACT_SUBVECTOR, Dl, in LowerSTORE()
4060 DAG.getNode(ISD::EXTRACT_SUBVECTOR, Dl, in LowerSTORE()
4218 case ISD::EXTRACT_SUBVECTOR: in LowerOperation()
7946 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
7952 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
7957 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
7960 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
[all …]
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 789 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand); in X86TargetLowering()
1366 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); in X86TargetLowering()
1470 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in X86TargetLowering()
1681 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); in X86TargetLowering()
1850 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in X86TargetLowering()
1976 setTargetDAGCombine(ISD::EXTRACT_SUBVECTOR); in X86TargetLowering()
4842 if (Opcode == ISD::EXTRACT_SUBVECTOR) in isTargetShuffleSplat()
5185 if (UI->getOpcode() != ISD::EXTRACT_SUBVECTOR || !UI->hasOneUse() || in shouldReduceLoadWidth()
5257 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
5832 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx); in extractSubVector()
[all …]
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 661 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand); in X86TargetLowering()
1099 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in X86TargetLowering()
1389 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in X86TargetLowering()
1392 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); in X86TargetLowering()
4161 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
4444 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx); in extractSubVector()
4598 return (WideOpVT == OpVT) ? V : DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, in insert1BitVector()
6041 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec, in LowerBUILD_VECTORvXi1()
6088 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec, in LowerBUILD_VECTORvXi1()
8668 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ExtVT, V, in lowerVectorShuffleAsBroadcast()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 780 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand); in X86TargetLowering()
1338 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); in X86TargetLowering()
1439 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in X86TargetLowering()
1611 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); in X86TargetLowering()
1756 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in X86TargetLowering()
1989 setTargetDAGCombine(ISD::EXTRACT_SUBVECTOR); in X86TargetLowering()
5046 if (UI->getOpcode() != ISD::EXTRACT_SUBVECTOR || !UI->hasOneUse() || in shouldReduceLoadWidth()
5118 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
5641 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx); in extractSubVector()
5847 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, Op, ZeroIdx); in insert1BitVector()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLoweringHVX.cpp | 99 setOperationAction(ISD::EXTRACT_SUBVECTOR, T, Custom); in initializeHVXLowering()
190 setOperationAction(ISD::EXTRACT_SUBVECTOR, BoolV, Custom); in initializeHVXLowering()
1567 case ISD::EXTRACT_SUBVECTOR: return LowerHvxExtractSubvector(Op, DAG); in LowerHvxOperation()
|