Searched refs:FADD_D (Results 1 – 17 of 17) sorted by relevance
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ |
D | floating_point_vec_arithmetic_operations.mir | 65 ; P5600: [[FADD_D:%[0-9]+]]:msa128d = FADD_D [[LD_D]], [[LD_D1]] 66 ; P5600: ST_D [[FADD_D]], [[COPY2]], 0 :: (store 16 into %ir.c)
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
D | RISCVInstrInfoD.td | 99 def FADD_D : FPALUD_rr_frm<0b0000001, "fadd.d">; 100 def : FPALUDDynFrmAlias<FADD_D, "fadd.d">; 245 def : PatFpr64Fpr64DynFrm<fadd, FADD_D>;
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/external/llvm-project/llvm/lib/Target/RISCV/ |
D | RISCVInstrInfoD.td | 97 def FADD_D : FPALUD_rr_frm<0b0000001, "fadd.d">, 99 def : FPALUDDynFrmAlias<FADD_D, "fadd.d">; 252 def : PatFpr64Fpr64DynFrm<fadd, FADD_D>;
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/external/mesa3d/src/mesa/x86/ |
D | assyntax.h | 689 #define FADD_D(a) CHOICE(faddl a, faddl a, faddd a) macro 1402 #define FADD_D(a) fadd D_(a) macro
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/external/capstone/arch/Mips/ |
D | MipsGenAsmWriter.inc | 699 134236265U, // FADD_D 2488 0U, // FADD_D
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D | MipsGenDisassemblerTables.inc | 2858 /* 9518 */ MCD_OPC_Decode, 170, 5, 140, 1, // Opcode: FADD_D
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/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
D | MipsGenMCCodeEmitter.inc | 1475 UINT64_C(2015363099), // FADD_D 8645 case Mips::FADD_D: 10937 CEFBS_HasStdEnc_HasMSA, // FADD_D = 1462
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D | MipsGenAsmWriter.inc | 2703 268454225U, // FADD_D 5457 0U, // FADD_D
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D | MipsGenFastISel.inc | 1493 return fastEmitInst_rr(Mips::FADD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
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D | MipsGenInstrInfo.inc | 1477 FADD_D = 1462, 6323 …<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1462 = FADD_D
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D | MipsGenDisassemblerTables.inc | 5180 /* 11794 */ MCD::OPC_Decode, 182, 11, 128, 2, // Opcode: FADD_D
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D | MipsGenAsmMatcher.inc | 6579 …{ 4094 /* fadd.d */, Mips::FADD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMF…
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D | MipsGenGlobalISel.inc | 21796 …4] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FADD_D:{ *:[v2f64] } MSA1… 21797 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D,
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D | MipsGenDAGISel.inc | 27443 /* 51901*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FADD_D), 0, 27446 … // Dst: (FADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
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/external/llvm/lib/Target/Mips/ |
D | MipsMSAInstrInfo.td | 2983 def FADD_D : FADD_D_ENC, FADD_D_DESC;
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/external/llvm-project/llvm/lib/Target/Mips/ |
D | MipsMSAInstrInfo.td | 3029 def FADD_D : FADD_D_ENC, FADD_D_DESC;
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
D | MipsMSAInstrInfo.td | 3009 def FADD_D : FADD_D_ENC, FADD_D_DESC;
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