Searched refs:FDIVD (Results 1 – 16 of 16) sorted by relevance
| /external/llvm-project/llvm/lib/Target/Sparc/ |
| D | LeonFeatures.td | 58 "LEON erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD instructions with NOPs and floating-point store"
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| D | LeonPasses.cpp | 142 if (Opcode == SP::FSQRTD || Opcode == SP::FDIVD) { in runOnMachineFunction()
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| D | DelaySlotFiller.cpp | 281 Opcode >= SP::FDIVD && Opcode <= SP::FSQRTD) in delayHasHazard()
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| D | SparcInstrInfo.td | 1275 // this will be promoted to use FDIVD with doubles instead.
1281 def FDIVD : F3_3<2, 0b110100, 0b001001110,
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | LeonFeatures.td | 58 "LEON erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD instructions with NOPs and floating-point store"
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| D | LeonPasses.cpp | 143 if (Opcode == SP::FSQRTD || Opcode == SP::FDIVD) { in runOnMachineFunction()
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| D | DelaySlotFiller.cpp | 281 Opcode >= SP::FDIVD && Opcode <= SP::FSQRTD) in delayHasHazard()
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| D | SparcInstrInfo.td | 1275 // this will be promoted to use FDIVD with doubles instead.
1281 def FDIVD : F3_3<2, 0b110100, 0b001001110,
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| /external/llvm/lib/Target/Sparc/ |
| D | LeonPasses.cpp | 374 Opcode = SP::FDIVD; in runOnMachineFunction()
382 if (Opcode == SP::FSQRTD || Opcode == SP::FDIVD) { in runOnMachineFunction()
658 NextOpcode == SP::FMULD || NextOpcode == SP::FDIVD) { in runOnMachineFunction()
895 case SP::FDIVD: in runOnMachineFunction()
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| D | LeonFeatures.td | 72 "LEON3 erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD "
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| D | DelaySlotFiller.cpp | 284 Opcode >= SP::FDIVD && Opcode <= SP::FSQRTD) in delayHasHazard()
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| D | SparcInstrInfo.td | 1269 // this will be promoted to use FDIVD with doubles instead.
1275 def FDIVD : F3_3<2, 0b110100, 0b001001110,
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeSPARC_common.c | 143 #define FDIVD (OPC1(0x2) | OPC3(0x34) | DOP(0x4e)) macro
1225 …FAIL_IF(push_inst(compiler, SELECT_FOP(op, FDIVS, FDIVD) | FD(dst_r) | FS1(src1) | FS2(src2), MOVA… in sljit_emit_fop2()
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| /external/capstone/arch/Sparc/ |
| D | SparcGenDisassemblerTables.inc | 628 /* 2417 */ MCD_OPC_Decode, 165, 1, 27, // Opcode: FDIVD
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| D | SparcGenAsmWriter.inc | 186 4960U, // FDIVD
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| /external/llvm-project/llvm/lib/Target/VE/ |
| D | VEInstrInfo.td | 1354 defm FDIVD : RRFm<"fdiv.d", 0x5D, I64, f64, fdiv>;
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