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Searched refs:FDIV_D (Results 1 – 20 of 20) sorted by relevance

/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
Dfloating_point_vec_arithmetic_operations.mir245 ; P5600: [[FDIV_D:%[0-9]+]]:msa128d = FDIV_D [[LD_D]], [[LD_D1]]
246 ; P5600: ST_D [[FDIV_D]], [[COPY2]], 0 :: (store 16 into %ir.c)
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrInfoD.td105 def FDIV_D : FPALUD_rr_frm<0b0001101, "fdiv.d">;
106 def : FPALUDDynFrmAlias<FDIV_D, "fdiv.d">;
248 def : PatFpr64Fpr64DynFrm<fdiv, FDIV_D>;
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfoD.td106 def FDIV_D : FPALUD_rr_frm<0b0001101, "fdiv.d">,
108 def : FPALUDDynFrmAlias<FDIV_D, "fdiv.d">;
255 def : PatFpr64Fpr64DynFrm<fdiv, FDIV_D>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsScheduleP5600.td483 def : InstRW<[P5600WriteFPUDivD], (instregex "^FDIV_D$")>;
DMipsMSAInstrInfo.td3048 def FDIV_D : FDIV_D_ENC, FDIV_D_DESC;
/external/llvm-project/llvm/lib/Target/Mips/
DMipsScheduleP5600.td484 def : InstRW<[P5600WriteFPUDivD], (instregex "^FDIV_D$")>;
DMipsMSAInstrInfo.td3068 def FDIV_D : FDIV_D_ENC, FDIV_D_DESC;
/external/mesa3d/src/mesa/x86/
Dassyntax.h709 #define FDIV_D(a) CHOICE(fdivl a, fdivl a, fdivd a) macro
1422 #define FDIV_D(a) fdiv D_(a) macro
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenSubtargetInfo.inc911 {DBGFIELD("FDIV_D") 1, false, false, 19, 2, 5, 1, 0, 0}, // #651
2595 {DBGFIELD("FDIV_D") 1, false, false, 59, 3, 12, 1, 0, 0}, // #651
DMipsGenMCCodeEmitter.inc1513 UINT64_C(2027946011), // FDIV_D
8669 case Mips::FDIV_D:
10975 CEFBS_HasStdEnc_HasMSA, // FDIV_D = 1500
DMipsGenAsmWriter.inc2741 268455821U, // FDIV_D
5495 0U, // FDIV_D
DMipsGenFastISel.inc1553 return fastEmitInst_rr(Mips::FDIV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
DMipsGenInstrInfo.inc1515 FDIV_D = 1500,
3431 FDIV_D = 651,
6361 …0, 3, 1, 4, 651, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1500 = FDIV_D
DMipsGenDisassemblerTables.inc5198 /* 11884 */ MCD::OPC_Decode, 220, 11, 128, 2, // Opcode: FDIV_D
DMipsGenAsmMatcher.inc6605 …{ 4288 /* fdiv.d */, Mips::FDIV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMF…
DMipsGenGlobalISel.inc22463 …4] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FDIV_D:{ *:[v2f64] } MSA1…
22464 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D,
DMipsGenDAGISel.inc27692 /* 52370*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FDIV_D), 0,
27695 … // Dst: (FDIV_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc735 134237862U, // FDIV_D
2524 0U, // FDIV_D
DMipsGenDisassemblerTables.inc2876 /* 9596 */ MCD_OPC_Decode, 206, 5, 140, 1, // Opcode: FDIV_D
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td3022 def FDIV_D : FDIV_D_ENC, FDIV_D_DESC;