Searched refs:FMUL_D (Results 1 – 17 of 17) sorted by relevance
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ |
D | floating_point_vec_arithmetic_operations.mir | 185 ; P5600: [[FMUL_D:%[0-9]+]]:msa128d = FMUL_D [[LD_D]], [[LD_D1]] 186 ; P5600: ST_D [[FMUL_D]], [[COPY2]], 0 :: (store 16 into %ir.c)
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
D | RISCVInstrInfoD.td | 103 def FMUL_D : FPALUD_rr_frm<0b0001001, "fmul.d">; 104 def : FPALUDDynFrmAlias<FMUL_D, "fmul.d">; 247 def : PatFpr64Fpr64DynFrm<fmul, FMUL_D>;
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/external/llvm-project/llvm/lib/Target/RISCV/ |
D | RISCVInstrInfoD.td | 103 def FMUL_D : FPALUD_rr_frm<0b0001001, "fmul.d">, 105 def : FPALUDDynFrmAlias<FMUL_D, "fmul.d">; 254 def : PatFpr64Fpr64DynFrm<fmul, FMUL_D>;
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/external/mesa3d/src/mesa/x86/ |
D | assyntax.h | 750 #define FMUL_D(a) CHOICE(fmull a, fmull a, fmuld a) macro 1463 #define FMUL_D(a) fmul D_(a) macro
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/external/capstone/arch/Mips/ |
D | MipsGenAsmWriter.inc | 792 134236826U, // FMUL_D 2581 0U, // FMUL_D
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D | MipsGenDisassemblerTables.inc | 2870 /* 9570 */ MCD_OPC_Decode, 135, 6, 140, 1, // Opcode: FMUL_D
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/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
D | MipsGenMCCodeEmitter.inc | 1575 UINT64_C(2023751707), // FMUL_D 8683 case Mips::FMUL_D: 11037 CEFBS_HasStdEnc_HasMSA, // FMUL_D = 1562
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D | MipsGenAsmWriter.inc | 2803 268454786U, // FMUL_D 5557 0U, // FMUL_D
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D | MipsGenFastISel.inc | 1613 return fastEmitInst_rr(Mips::FMUL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
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D | MipsGenInstrInfo.inc | 1577 FMUL_D = 1562, 6423 …2, 3, 1, 4, 654, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1562 = FMUL_D
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D | MipsGenDisassemblerTables.inc | 5192 /* 11854 */ MCD::OPC_Decode, 154, 12, 128, 2, // Opcode: FMUL_D
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D | MipsGenAsmMatcher.inc | 6652 …{ 4618 /* fmul.d */, Mips::FMUL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMF…
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D | MipsGenGlobalISel.inc | 22255 …4] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMUL_D:{ *:[v2f64] } MSA1… 22256 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D,
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D | MipsGenDAGISel.inc | 27798 /* 52564*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FMUL_D), 0, 27801 … // Dst: (FMUL_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
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/external/llvm/lib/Target/Mips/ |
D | MipsMSAInstrInfo.td | 3079 def FMUL_D : FMUL_D_ENC, FMUL_D_DESC;
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/external/llvm-project/llvm/lib/Target/Mips/ |
D | MipsMSAInstrInfo.td | 3125 def FMUL_D : FMUL_D_ENC, FMUL_D_DESC;
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
D | MipsMSAInstrInfo.td | 3105 def FMUL_D : FMUL_D_ENC, FMUL_D_DESC;
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