| /external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/ |
| D | legalize-frint.mir | 31 ; NOFP16: [[FRINT:%[0-9]+]]:_(s32) = G_FRINT [[COPY]]
32 ; NOFP16: $s0 = COPY [[FRINT]](s32)
37 ; FP16: [[FRINT:%[0-9]+]]:_(s32) = G_FRINT [[COPY]]
38 ; FP16: $s0 = COPY [[FRINT]](s32)
58 ; NOFP16: [[FRINT:%[0-9]+]]:_(s64) = G_FRINT [[COPY]]
59 ; NOFP16: $d0 = COPY [[FRINT]](s64)
64 ; FP16: [[FRINT:%[0-9]+]]:_(s64) = G_FRINT [[COPY]]
65 ; FP16: $d0 = COPY [[FRINT]](s64)
85 ; NOFP16: [[FRINT:%[0-9]+]]:_(<4 x s32>) = G_FRINT [[COPY]]
86 ; NOFP16: $q0 = COPY [[FRINT]](<4 x s32>)
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| D | legalize-frint.mir | 15 ; SI: [[FRINT:%[0-9]+]]:_(s32) = G_FRINT [[FPEXT]]
16 ; SI: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FRINT]](s32)
23 ; CI: [[FRINT:%[0-9]+]]:_(s32) = G_FRINT [[FPEXT]]
24 ; CI: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FRINT]](s32)
73 ; CI: [[FRINT:%[0-9]+]]:_(s64) = G_FRINT [[COPY]]
74 ; CI: $vgpr0_vgpr1 = COPY [[FRINT]](s64)
106 ; SI: [[FRINT:%[0-9]+]]:_(s32) = G_FRINT [[UV]]
108 ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FRINT]](s32), [[FRINT1]](s32)
113 ; CI: [[FRINT:%[0-9]+]]:_(s32) = G_FRINT [[UV]]
115 ; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FRINT]](s32), [[FRINT1]](s32)
[all …]
|
| D | regbankselect-frint.mir | 15 ; CHECK: [[FRINT:%[0-9]+]]:vgpr(s32) = G_FRINT [[COPY1]]
29 ; CHECK: [[FRINT:%[0-9]+]]:vgpr(s32) = G_FRINT [[COPY]]
|
| D | inst-select-frint.s16.mir | 18 ; GCN: [[FRINT:%[0-9]+]]:sreg_32(s16) = G_FRINT [[TRUNC]]
19 ; GCN: [[COPY1:%[0-9]+]]:sreg_32(s32) = COPY [[FRINT]](s16)
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 526 FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR, enumerator
|
| D | BasicTTIImpl.h | 794 ISDs.push_back(ISD::FRINT); in getIntrinsicInstrCost()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | ConstrainedOps.def | 78 FUNCTION(rint, 1, 1, experimental_constrained_rint, FRINT)
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 642 FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR, enumerator
|
| /external/llvm-project/llvm/include/llvm/IR/ |
| D | ConstrainedOps.def | 92 DAG_FUNCTION(rint, 1, 1, experimental_constrained_rint, FRINT)
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 808 FRINT, enumerator
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCTRLoops.cpp | 305 case Intrinsic::rint: Opcode = ISD::FRINT; break; in mightUseCTR()
360 Opcode = ISD::FRINT; break; in mightUseCTR()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCTargetTransformInfo.cpp | 315 case Intrinsic::rint: Opcode = ISD::FRINT; break; in mightUseCTR()
376 Opcode = ISD::FRINT; break; in mightUseCTR()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedM1.td | 255 def : InstRW<[M1WriteFCVT3], (instregex "^FRINT.+r")>;
316 def : InstRW<[M1WriteFCVT3], (instregex "^FRINT[AIMNPXZ]v")>;
|
| D | AArch64SchedA57.td | 486 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT[AIMNPXZ](v2f32)")>;
488 def : InstRW<[A57Write_5cyc_2V], (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;
559 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT.+r")>;
|
| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCTargetTransformInfo.cpp | 474 case Intrinsic::rint: Opcode = ISD::FRINT; break; in mightUseCTR()
583 Opcode = ISD::FRINT; break; in mightUseCTR()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64SchedA57.td | 490 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT[AIMNPXZ](v2f32)")>;
492 def : InstRW<[A57Write_5cyc_2V], (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;
563 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT.+r")>;
|
| D | AArch64SchedTSV110.td | 480 def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FRINT.+r")>;
670 def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FRINT[AIMNPXZ]v")>;
|
| D | AArch64SchedExynosM3.td | 542 def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT.+r")>;
657 def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>;
|
| D | AArch64SchedFalkorDetails.td | 592 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FRINT(A|I|M|N|P|X|Z)v2f32$")>;
617 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^FRINT(A|I|M|N|P|X|Z)(v2f64|v4f32)$")>;
1123 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FRINT(A|I|M|N|P|X|Z)(S|D)r$")>;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedA57.td | 489 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT[AIMNPXZ](v2f32)")>;
491 def : InstRW<[A57Write_5cyc_2V], (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;
562 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT.+r")>;
|
| D | AArch64SchedExynosM3.td | 541 def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT.+r")>;
656 def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>;
|
| D | AArch64SchedFalkorDetails.td | 592 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FRINT(A|I|M|N|P|X|Z)v2f32$")>;
617 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^FRINT(A|I|M|N|P|X|Z)(v2f64|v4f32)$")>;
1123 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FRINT(A|I|M|N|P|X|Z)(S|D)r$")>;
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 165 case ISD::FRINT: return "frint"; in getOperationName()
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 87 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT}) in WebAssemblyTargetLowering()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 244 setOperationAction(ISD::FRINT, MVT::f32, Legal); in AMDGPUTargetLowering()
279 setOperationAction(ISD::FRINT, MVT::f64, Custom); in AMDGPUTargetLowering()
422 setOperationAction(ISD::FRINT, VT, Expand); in AMDGPUTargetLowering()
715 case ISD::FRINT: return LowerFRINT(Op, DAG); in LowerOperation()
1723 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0)); in LowerFNEARBYINT()
|