| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 538 FSINCOS, enumerator
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 666 FSINCOS, enumerator
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 842 FSINCOS, enumerator
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 161 case ISD::FSINCOS: return "fsincos"; in getOperationName()
|
| D | LegalizeDAG.cpp | 2190 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS) in useSinCos()
3154 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) || in ExpandNode()
3158 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0)); in ExpandNode()
3827 case ISD::FSINCOS: in ConvertNodeToLibcall()
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 81 for (auto Op : {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOWI, ISD::FPOW, in WebAssemblyTargetLowering()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 200 case ISD::FSINCOS: return "fsincos"; in getOperationName()
|
| D | LegalizeDAG.cpp | 2269 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS) in useSinCos()
3197 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) || in ExpandNode()
3201 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0)); in ExpandNode()
3972 case ISD::FSINCOS: in ConvertNodeToLibcall()
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 202 case ISD::FSINCOS: return "fsincos"; in getOperationName()
|
| D | LegalizeDAG.cpp | 2326 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS) in useSinCos()
3331 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) || in ExpandNode()
3335 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0)); in ExpandNode()
4142 case ISD::FSINCOS: in ConvertNodeToLibcall()
|
| /external/llvm-project/llvm/test/CodeGen/RISCV/ |
| D | float-intrinsics.ll | 104 ; The sin+cos combination results in an FSINCOS SelectionDAG node.
|
| D | double-intrinsics.ll | 106 ; The sin+cos combination results in an FSINCOS SelectionDAG node.
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 155 setOperationAction(ISD::FSINCOS, MVT::f128, Expand); in AArch64TargetLowering()
283 setOperationAction(ISD::FSINCOS, MVT::f16, Promote); in AArch64TargetLowering()
329 setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand); in AArch64TargetLowering()
361 setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand); in AArch64TargetLowering()
403 setOperationAction(ISD::FSINCOS, MVT::f64, Custom); in AArch64TargetLowering()
404 setOperationAction(ISD::FSINCOS, MVT::f32, Custom); in AArch64TargetLowering()
406 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in AArch64TargetLowering()
407 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in AArch64TargetLowering()
539 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand); in AArch64TargetLowering()
2402 case ISD::FSINCOS: in LowerOperation()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ScheduleAtom.td | 891 def : InstRW<[AtomWrite01_174], (instrs FSINCOS, FSIN, FCOS)>;
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ScheduleAtom.td | 894 def : InstRW<[AtomWrite01_174], (instrs FSINCOS, FSIN, FCOS)>;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 270 setOperationAction(ISD::FSINCOS, MVT::f128, Expand); in AArch64TargetLowering()
414 setOperationAction(ISD::FSINCOS, MVT::f16, Promote); in AArch64TargetLowering()
415 setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand); in AArch64TargetLowering()
416 setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand); in AArch64TargetLowering()
558 setOperationAction(ISD::FSINCOS, MVT::f64, Custom); in AArch64TargetLowering()
559 setOperationAction(ISD::FSINCOS, MVT::f32, Custom); in AArch64TargetLowering()
561 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in AArch64TargetLowering()
562 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in AArch64TargetLowering()
721 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand); in AArch64TargetLowering()
3258 case ISD::FSINCOS: in LowerOperation()
|
| /external/llvm-project/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1625 setOperationAction(ISD::FSINCOS, MVT::f128, Expand); in SparcTargetLowering()
1630 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in SparcTargetLowering()
1635 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in SparcTargetLowering()
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1668 setOperationAction(ISD::FSINCOS, MVT::f128, Expand); in SparcTargetLowering()
1673 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in SparcTargetLowering()
1678 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in SparcTargetLowering()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1618 setOperationAction(ISD::FSINCOS, MVT::f128, Expand); in SparcTargetLowering()
1623 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in SparcTargetLowering()
1628 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in SparcTargetLowering()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 94 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA}) in WebAssemblyTargetLowering()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 392 setOperationAction(ISD::FSINCOS, MVT::f128, Expand); in AArch64TargetLowering()
546 setOperationAction(ISD::FSINCOS, MVT::f16, Promote); in AArch64TargetLowering()
547 setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand); in AArch64TargetLowering()
548 setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand); in AArch64TargetLowering()
752 setOperationAction(ISD::FSINCOS, MVT::f64, Custom); in AArch64TargetLowering()
753 setOperationAction(ISD::FSINCOS, MVT::f32, Custom); in AArch64TargetLowering()
755 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in AArch64TargetLowering()
756 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in AArch64TargetLowering()
924 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand); in AArch64TargetLowering()
4266 case ISD::FSINCOS: in LowerOperation()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1437 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1486 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS, in HexagonTargetLowering()
|
| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1570 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1619 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS, in HexagonTargetLowering()
|
| /external/mesa3d/src/mesa/x86/ |
| D | assyntax.h | 766 #define FSINCOS CHOICE(fsincos, fsincos, fsincos) macro
1479 #define FSINCOS fsincos macro
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1887 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1949 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS, in HexagonTargetLowering()
|