1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ 3; RUN: | FileCheck -check-prefix=RV32IF %s 4; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ 5; RUN: | FileCheck -check-prefix=RV32IF %s 6; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ 7; RUN: | FileCheck -check-prefix=RV64IF %s 8; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ 9; RUN: | FileCheck -check-prefix=RV64IF %s 10 11declare float @llvm.sqrt.f32(float) 12 13define float @sqrt_f32(float %a) nounwind { 14; RV32IF-LABEL: sqrt_f32: 15; RV32IF: # %bb.0: 16; RV32IF-NEXT: fmv.w.x ft0, a0 17; RV32IF-NEXT: fsqrt.s ft0, ft0 18; RV32IF-NEXT: fmv.x.w a0, ft0 19; RV32IF-NEXT: ret 20; 21; RV64IF-LABEL: sqrt_f32: 22; RV64IF: # %bb.0: 23; RV64IF-NEXT: fmv.w.x ft0, a0 24; RV64IF-NEXT: fsqrt.s ft0, ft0 25; RV64IF-NEXT: fmv.x.w a0, ft0 26; RV64IF-NEXT: ret 27 %1 = call float @llvm.sqrt.f32(float %a) 28 ret float %1 29} 30 31declare float @llvm.powi.f32(float, i32) 32 33define float @powi_f32(float %a, i32 %b) nounwind { 34; RV32IF-LABEL: powi_f32: 35; RV32IF: # %bb.0: 36; RV32IF-NEXT: addi sp, sp, -16 37; RV32IF-NEXT: sw ra, 12(sp) 38; RV32IF-NEXT: call __powisf2 39; RV32IF-NEXT: lw ra, 12(sp) 40; RV32IF-NEXT: addi sp, sp, 16 41; RV32IF-NEXT: ret 42; 43; RV64IF-LABEL: powi_f32: 44; RV64IF: # %bb.0: 45; RV64IF-NEXT: addi sp, sp, -16 46; RV64IF-NEXT: sd ra, 8(sp) 47; RV64IF-NEXT: sext.w a1, a1 48; RV64IF-NEXT: call __powisf2 49; RV64IF-NEXT: ld ra, 8(sp) 50; RV64IF-NEXT: addi sp, sp, 16 51; RV64IF-NEXT: ret 52 %1 = call float @llvm.powi.f32(float %a, i32 %b) 53 ret float %1 54} 55 56declare float @llvm.sin.f32(float) 57 58define float @sin_f32(float %a) nounwind { 59; RV32IF-LABEL: sin_f32: 60; RV32IF: # %bb.0: 61; RV32IF-NEXT: addi sp, sp, -16 62; RV32IF-NEXT: sw ra, 12(sp) 63; RV32IF-NEXT: call sinf 64; RV32IF-NEXT: lw ra, 12(sp) 65; RV32IF-NEXT: addi sp, sp, 16 66; RV32IF-NEXT: ret 67; 68; RV64IF-LABEL: sin_f32: 69; RV64IF: # %bb.0: 70; RV64IF-NEXT: addi sp, sp, -16 71; RV64IF-NEXT: sd ra, 8(sp) 72; RV64IF-NEXT: call sinf 73; RV64IF-NEXT: ld ra, 8(sp) 74; RV64IF-NEXT: addi sp, sp, 16 75; RV64IF-NEXT: ret 76 %1 = call float @llvm.sin.f32(float %a) 77 ret float %1 78} 79 80declare float @llvm.cos.f32(float) 81 82define float @cos_f32(float %a) nounwind { 83; RV32IF-LABEL: cos_f32: 84; RV32IF: # %bb.0: 85; RV32IF-NEXT: addi sp, sp, -16 86; RV32IF-NEXT: sw ra, 12(sp) 87; RV32IF-NEXT: call cosf 88; RV32IF-NEXT: lw ra, 12(sp) 89; RV32IF-NEXT: addi sp, sp, 16 90; RV32IF-NEXT: ret 91; 92; RV64IF-LABEL: cos_f32: 93; RV64IF: # %bb.0: 94; RV64IF-NEXT: addi sp, sp, -16 95; RV64IF-NEXT: sd ra, 8(sp) 96; RV64IF-NEXT: call cosf 97; RV64IF-NEXT: ld ra, 8(sp) 98; RV64IF-NEXT: addi sp, sp, 16 99; RV64IF-NEXT: ret 100 %1 = call float @llvm.cos.f32(float %a) 101 ret float %1 102} 103 104; The sin+cos combination results in an FSINCOS SelectionDAG node. 105define float @sincos_f32(float %a) nounwind { 106; RV32IF-LABEL: sincos_f32: 107; RV32IF: # %bb.0: 108; RV32IF-NEXT: addi sp, sp, -16 109; RV32IF-NEXT: sw ra, 12(sp) 110; RV32IF-NEXT: sw s0, 8(sp) 111; RV32IF-NEXT: mv s0, a0 112; RV32IF-NEXT: call sinf 113; RV32IF-NEXT: fmv.w.x ft0, a0 114; RV32IF-NEXT: fsw ft0, 4(sp) 115; RV32IF-NEXT: mv a0, s0 116; RV32IF-NEXT: call cosf 117; RV32IF-NEXT: fmv.w.x ft0, a0 118; RV32IF-NEXT: flw ft1, 4(sp) 119; RV32IF-NEXT: fadd.s ft0, ft1, ft0 120; RV32IF-NEXT: fmv.x.w a0, ft0 121; RV32IF-NEXT: lw s0, 8(sp) 122; RV32IF-NEXT: lw ra, 12(sp) 123; RV32IF-NEXT: addi sp, sp, 16 124; RV32IF-NEXT: ret 125; 126; RV64IF-LABEL: sincos_f32: 127; RV64IF: # %bb.0: 128; RV64IF-NEXT: addi sp, sp, -32 129; RV64IF-NEXT: sd ra, 24(sp) 130; RV64IF-NEXT: sd s0, 16(sp) 131; RV64IF-NEXT: mv s0, a0 132; RV64IF-NEXT: call sinf 133; RV64IF-NEXT: fmv.w.x ft0, a0 134; RV64IF-NEXT: fsw ft0, 12(sp) 135; RV64IF-NEXT: mv a0, s0 136; RV64IF-NEXT: call cosf 137; RV64IF-NEXT: fmv.w.x ft0, a0 138; RV64IF-NEXT: flw ft1, 12(sp) 139; RV64IF-NEXT: fadd.s ft0, ft1, ft0 140; RV64IF-NEXT: fmv.x.w a0, ft0 141; RV64IF-NEXT: ld s0, 16(sp) 142; RV64IF-NEXT: ld ra, 24(sp) 143; RV64IF-NEXT: addi sp, sp, 32 144; RV64IF-NEXT: ret 145 %1 = call float @llvm.sin.f32(float %a) 146 %2 = call float @llvm.cos.f32(float %a) 147 %3 = fadd float %1, %2 148 ret float %3 149} 150 151declare float @llvm.pow.f32(float, float) 152 153define float @pow_f32(float %a, float %b) nounwind { 154; RV32IF-LABEL: pow_f32: 155; RV32IF: # %bb.0: 156; RV32IF-NEXT: addi sp, sp, -16 157; RV32IF-NEXT: sw ra, 12(sp) 158; RV32IF-NEXT: call powf 159; RV32IF-NEXT: lw ra, 12(sp) 160; RV32IF-NEXT: addi sp, sp, 16 161; RV32IF-NEXT: ret 162; 163; RV64IF-LABEL: pow_f32: 164; RV64IF: # %bb.0: 165; RV64IF-NEXT: addi sp, sp, -16 166; RV64IF-NEXT: sd ra, 8(sp) 167; RV64IF-NEXT: call powf 168; RV64IF-NEXT: ld ra, 8(sp) 169; RV64IF-NEXT: addi sp, sp, 16 170; RV64IF-NEXT: ret 171 %1 = call float @llvm.pow.f32(float %a, float %b) 172 ret float %1 173} 174 175declare float @llvm.exp.f32(float) 176 177define float @exp_f32(float %a) nounwind { 178; RV32IF-LABEL: exp_f32: 179; RV32IF: # %bb.0: 180; RV32IF-NEXT: addi sp, sp, -16 181; RV32IF-NEXT: sw ra, 12(sp) 182; RV32IF-NEXT: call expf 183; RV32IF-NEXT: lw ra, 12(sp) 184; RV32IF-NEXT: addi sp, sp, 16 185; RV32IF-NEXT: ret 186; 187; RV64IF-LABEL: exp_f32: 188; RV64IF: # %bb.0: 189; RV64IF-NEXT: addi sp, sp, -16 190; RV64IF-NEXT: sd ra, 8(sp) 191; RV64IF-NEXT: call expf 192; RV64IF-NEXT: ld ra, 8(sp) 193; RV64IF-NEXT: addi sp, sp, 16 194; RV64IF-NEXT: ret 195 %1 = call float @llvm.exp.f32(float %a) 196 ret float %1 197} 198 199declare float @llvm.exp2.f32(float) 200 201define float @exp2_f32(float %a) nounwind { 202; RV32IF-LABEL: exp2_f32: 203; RV32IF: # %bb.0: 204; RV32IF-NEXT: addi sp, sp, -16 205; RV32IF-NEXT: sw ra, 12(sp) 206; RV32IF-NEXT: call exp2f 207; RV32IF-NEXT: lw ra, 12(sp) 208; RV32IF-NEXT: addi sp, sp, 16 209; RV32IF-NEXT: ret 210; 211; RV64IF-LABEL: exp2_f32: 212; RV64IF: # %bb.0: 213; RV64IF-NEXT: addi sp, sp, -16 214; RV64IF-NEXT: sd ra, 8(sp) 215; RV64IF-NEXT: call exp2f 216; RV64IF-NEXT: ld ra, 8(sp) 217; RV64IF-NEXT: addi sp, sp, 16 218; RV64IF-NEXT: ret 219 %1 = call float @llvm.exp2.f32(float %a) 220 ret float %1 221} 222 223declare float @llvm.log.f32(float) 224 225define float @log_f32(float %a) nounwind { 226; RV32IF-LABEL: log_f32: 227; RV32IF: # %bb.0: 228; RV32IF-NEXT: addi sp, sp, -16 229; RV32IF-NEXT: sw ra, 12(sp) 230; RV32IF-NEXT: call logf 231; RV32IF-NEXT: lw ra, 12(sp) 232; RV32IF-NEXT: addi sp, sp, 16 233; RV32IF-NEXT: ret 234; 235; RV64IF-LABEL: log_f32: 236; RV64IF: # %bb.0: 237; RV64IF-NEXT: addi sp, sp, -16 238; RV64IF-NEXT: sd ra, 8(sp) 239; RV64IF-NEXT: call logf 240; RV64IF-NEXT: ld ra, 8(sp) 241; RV64IF-NEXT: addi sp, sp, 16 242; RV64IF-NEXT: ret 243 %1 = call float @llvm.log.f32(float %a) 244 ret float %1 245} 246 247declare float @llvm.log10.f32(float) 248 249define float @log10_f32(float %a) nounwind { 250; RV32IF-LABEL: log10_f32: 251; RV32IF: # %bb.0: 252; RV32IF-NEXT: addi sp, sp, -16 253; RV32IF-NEXT: sw ra, 12(sp) 254; RV32IF-NEXT: call log10f 255; RV32IF-NEXT: lw ra, 12(sp) 256; RV32IF-NEXT: addi sp, sp, 16 257; RV32IF-NEXT: ret 258; 259; RV64IF-LABEL: log10_f32: 260; RV64IF: # %bb.0: 261; RV64IF-NEXT: addi sp, sp, -16 262; RV64IF-NEXT: sd ra, 8(sp) 263; RV64IF-NEXT: call log10f 264; RV64IF-NEXT: ld ra, 8(sp) 265; RV64IF-NEXT: addi sp, sp, 16 266; RV64IF-NEXT: ret 267 %1 = call float @llvm.log10.f32(float %a) 268 ret float %1 269} 270 271declare float @llvm.log2.f32(float) 272 273define float @log2_f32(float %a) nounwind { 274; RV32IF-LABEL: log2_f32: 275; RV32IF: # %bb.0: 276; RV32IF-NEXT: addi sp, sp, -16 277; RV32IF-NEXT: sw ra, 12(sp) 278; RV32IF-NEXT: call log2f 279; RV32IF-NEXT: lw ra, 12(sp) 280; RV32IF-NEXT: addi sp, sp, 16 281; RV32IF-NEXT: ret 282; 283; RV64IF-LABEL: log2_f32: 284; RV64IF: # %bb.0: 285; RV64IF-NEXT: addi sp, sp, -16 286; RV64IF-NEXT: sd ra, 8(sp) 287; RV64IF-NEXT: call log2f 288; RV64IF-NEXT: ld ra, 8(sp) 289; RV64IF-NEXT: addi sp, sp, 16 290; RV64IF-NEXT: ret 291 %1 = call float @llvm.log2.f32(float %a) 292 ret float %1 293} 294 295declare float @llvm.fma.f32(float, float, float) 296 297define float @fma_f32(float %a, float %b, float %c) nounwind { 298; RV32IF-LABEL: fma_f32: 299; RV32IF: # %bb.0: 300; RV32IF-NEXT: fmv.w.x ft0, a2 301; RV32IF-NEXT: fmv.w.x ft1, a1 302; RV32IF-NEXT: fmv.w.x ft2, a0 303; RV32IF-NEXT: fmadd.s ft0, ft2, ft1, ft0 304; RV32IF-NEXT: fmv.x.w a0, ft0 305; RV32IF-NEXT: ret 306; 307; RV64IF-LABEL: fma_f32: 308; RV64IF: # %bb.0: 309; RV64IF-NEXT: fmv.w.x ft0, a2 310; RV64IF-NEXT: fmv.w.x ft1, a1 311; RV64IF-NEXT: fmv.w.x ft2, a0 312; RV64IF-NEXT: fmadd.s ft0, ft2, ft1, ft0 313; RV64IF-NEXT: fmv.x.w a0, ft0 314; RV64IF-NEXT: ret 315 %1 = call float @llvm.fma.f32(float %a, float %b, float %c) 316 ret float %1 317} 318 319declare float @llvm.fmuladd.f32(float, float, float) 320 321define float @fmuladd_f32(float %a, float %b, float %c) nounwind { 322; RV32IF-LABEL: fmuladd_f32: 323; RV32IF: # %bb.0: 324; RV32IF-NEXT: fmv.w.x ft0, a2 325; RV32IF-NEXT: fmv.w.x ft1, a1 326; RV32IF-NEXT: fmv.w.x ft2, a0 327; RV32IF-NEXT: fmadd.s ft0, ft2, ft1, ft0 328; RV32IF-NEXT: fmv.x.w a0, ft0 329; RV32IF-NEXT: ret 330; 331; RV64IF-LABEL: fmuladd_f32: 332; RV64IF: # %bb.0: 333; RV64IF-NEXT: fmv.w.x ft0, a2 334; RV64IF-NEXT: fmv.w.x ft1, a1 335; RV64IF-NEXT: fmv.w.x ft2, a0 336; RV64IF-NEXT: fmadd.s ft0, ft2, ft1, ft0 337; RV64IF-NEXT: fmv.x.w a0, ft0 338; RV64IF-NEXT: ret 339 %1 = call float @llvm.fmuladd.f32(float %a, float %b, float %c) 340 ret float %1 341} 342 343declare float @llvm.fabs.f32(float) 344 345define float @fabs_f32(float %a) nounwind { 346; RV32IF-LABEL: fabs_f32: 347; RV32IF: # %bb.0: 348; RV32IF-NEXT: lui a1, 524288 349; RV32IF-NEXT: addi a1, a1, -1 350; RV32IF-NEXT: and a0, a0, a1 351; RV32IF-NEXT: ret 352; 353; RV64IF-LABEL: fabs_f32: 354; RV64IF: # %bb.0: 355; RV64IF-NEXT: lui a1, 524288 356; RV64IF-NEXT: addiw a1, a1, -1 357; RV64IF-NEXT: and a0, a0, a1 358; RV64IF-NEXT: ret 359 %1 = call float @llvm.fabs.f32(float %a) 360 ret float %1 361} 362 363declare float @llvm.minnum.f32(float, float) 364 365define float @minnum_f32(float %a, float %b) nounwind { 366; RV32IF-LABEL: minnum_f32: 367; RV32IF: # %bb.0: 368; RV32IF-NEXT: fmv.w.x ft0, a1 369; RV32IF-NEXT: fmv.w.x ft1, a0 370; RV32IF-NEXT: fmin.s ft0, ft1, ft0 371; RV32IF-NEXT: fmv.x.w a0, ft0 372; RV32IF-NEXT: ret 373; 374; RV64IF-LABEL: minnum_f32: 375; RV64IF: # %bb.0: 376; RV64IF-NEXT: fmv.w.x ft0, a1 377; RV64IF-NEXT: fmv.w.x ft1, a0 378; RV64IF-NEXT: fmin.s ft0, ft1, ft0 379; RV64IF-NEXT: fmv.x.w a0, ft0 380; RV64IF-NEXT: ret 381 %1 = call float @llvm.minnum.f32(float %a, float %b) 382 ret float %1 383} 384 385declare float @llvm.maxnum.f32(float, float) 386 387define float @maxnum_f32(float %a, float %b) nounwind { 388; RV32IF-LABEL: maxnum_f32: 389; RV32IF: # %bb.0: 390; RV32IF-NEXT: fmv.w.x ft0, a1 391; RV32IF-NEXT: fmv.w.x ft1, a0 392; RV32IF-NEXT: fmax.s ft0, ft1, ft0 393; RV32IF-NEXT: fmv.x.w a0, ft0 394; RV32IF-NEXT: ret 395; 396; RV64IF-LABEL: maxnum_f32: 397; RV64IF: # %bb.0: 398; RV64IF-NEXT: fmv.w.x ft0, a1 399; RV64IF-NEXT: fmv.w.x ft1, a0 400; RV64IF-NEXT: fmax.s ft0, ft1, ft0 401; RV64IF-NEXT: fmv.x.w a0, ft0 402; RV64IF-NEXT: ret 403 %1 = call float @llvm.maxnum.f32(float %a, float %b) 404 ret float %1 405} 406 407; TODO: FMINNAN and FMAXNAN aren't handled in 408; SelectionDAGLegalize::ExpandNode. 409 410; declare float @llvm.minimum.f32(float, float) 411 412; define float @fminimum_f32(float %a, float %b) nounwind { 413; %1 = call float @llvm.minimum.f32(float %a, float %b) 414; ret float %1 415; } 416 417; declare float @llvm.maximum.f32(float, float) 418 419; define float @fmaximum_f32(float %a, float %b) nounwind { 420; %1 = call float @llvm.maximum.f32(float %a, float %b) 421; ret float %1 422; } 423 424declare float @llvm.copysign.f32(float, float) 425 426define float @copysign_f32(float %a, float %b) nounwind { 427; RV32IF-LABEL: copysign_f32: 428; RV32IF: # %bb.0: 429; RV32IF-NEXT: fmv.w.x ft0, a1 430; RV32IF-NEXT: fmv.w.x ft1, a0 431; RV32IF-NEXT: fsgnj.s ft0, ft1, ft0 432; RV32IF-NEXT: fmv.x.w a0, ft0 433; RV32IF-NEXT: ret 434; 435; RV64IF-LABEL: copysign_f32: 436; RV64IF: # %bb.0: 437; RV64IF-NEXT: fmv.w.x ft0, a1 438; RV64IF-NEXT: fmv.w.x ft1, a0 439; RV64IF-NEXT: fsgnj.s ft0, ft1, ft0 440; RV64IF-NEXT: fmv.x.w a0, ft0 441; RV64IF-NEXT: ret 442 %1 = call float @llvm.copysign.f32(float %a, float %b) 443 ret float %1 444} 445 446declare float @llvm.floor.f32(float) 447 448define float @floor_f32(float %a) nounwind { 449; RV32IF-LABEL: floor_f32: 450; RV32IF: # %bb.0: 451; RV32IF-NEXT: addi sp, sp, -16 452; RV32IF-NEXT: sw ra, 12(sp) 453; RV32IF-NEXT: call floorf 454; RV32IF-NEXT: lw ra, 12(sp) 455; RV32IF-NEXT: addi sp, sp, 16 456; RV32IF-NEXT: ret 457; 458; RV64IF-LABEL: floor_f32: 459; RV64IF: # %bb.0: 460; RV64IF-NEXT: addi sp, sp, -16 461; RV64IF-NEXT: sd ra, 8(sp) 462; RV64IF-NEXT: call floorf 463; RV64IF-NEXT: ld ra, 8(sp) 464; RV64IF-NEXT: addi sp, sp, 16 465; RV64IF-NEXT: ret 466 %1 = call float @llvm.floor.f32(float %a) 467 ret float %1 468} 469 470declare float @llvm.ceil.f32(float) 471 472define float @ceil_f32(float %a) nounwind { 473; RV32IF-LABEL: ceil_f32: 474; RV32IF: # %bb.0: 475; RV32IF-NEXT: addi sp, sp, -16 476; RV32IF-NEXT: sw ra, 12(sp) 477; RV32IF-NEXT: call ceilf 478; RV32IF-NEXT: lw ra, 12(sp) 479; RV32IF-NEXT: addi sp, sp, 16 480; RV32IF-NEXT: ret 481; 482; RV64IF-LABEL: ceil_f32: 483; RV64IF: # %bb.0: 484; RV64IF-NEXT: addi sp, sp, -16 485; RV64IF-NEXT: sd ra, 8(sp) 486; RV64IF-NEXT: call ceilf 487; RV64IF-NEXT: ld ra, 8(sp) 488; RV64IF-NEXT: addi sp, sp, 16 489; RV64IF-NEXT: ret 490 %1 = call float @llvm.ceil.f32(float %a) 491 ret float %1 492} 493 494declare float @llvm.trunc.f32(float) 495 496define float @trunc_f32(float %a) nounwind { 497; RV32IF-LABEL: trunc_f32: 498; RV32IF: # %bb.0: 499; RV32IF-NEXT: addi sp, sp, -16 500; RV32IF-NEXT: sw ra, 12(sp) 501; RV32IF-NEXT: call truncf 502; RV32IF-NEXT: lw ra, 12(sp) 503; RV32IF-NEXT: addi sp, sp, 16 504; RV32IF-NEXT: ret 505; 506; RV64IF-LABEL: trunc_f32: 507; RV64IF: # %bb.0: 508; RV64IF-NEXT: addi sp, sp, -16 509; RV64IF-NEXT: sd ra, 8(sp) 510; RV64IF-NEXT: call truncf 511; RV64IF-NEXT: ld ra, 8(sp) 512; RV64IF-NEXT: addi sp, sp, 16 513; RV64IF-NEXT: ret 514 %1 = call float @llvm.trunc.f32(float %a) 515 ret float %1 516} 517 518declare float @llvm.rint.f32(float) 519 520define float @rint_f32(float %a) nounwind { 521; RV32IF-LABEL: rint_f32: 522; RV32IF: # %bb.0: 523; RV32IF-NEXT: addi sp, sp, -16 524; RV32IF-NEXT: sw ra, 12(sp) 525; RV32IF-NEXT: call rintf 526; RV32IF-NEXT: lw ra, 12(sp) 527; RV32IF-NEXT: addi sp, sp, 16 528; RV32IF-NEXT: ret 529; 530; RV64IF-LABEL: rint_f32: 531; RV64IF: # %bb.0: 532; RV64IF-NEXT: addi sp, sp, -16 533; RV64IF-NEXT: sd ra, 8(sp) 534; RV64IF-NEXT: call rintf 535; RV64IF-NEXT: ld ra, 8(sp) 536; RV64IF-NEXT: addi sp, sp, 16 537; RV64IF-NEXT: ret 538 %1 = call float @llvm.rint.f32(float %a) 539 ret float %1 540} 541 542declare float @llvm.nearbyint.f32(float) 543 544define float @nearbyint_f32(float %a) nounwind { 545; RV32IF-LABEL: nearbyint_f32: 546; RV32IF: # %bb.0: 547; RV32IF-NEXT: addi sp, sp, -16 548; RV32IF-NEXT: sw ra, 12(sp) 549; RV32IF-NEXT: call nearbyintf 550; RV32IF-NEXT: lw ra, 12(sp) 551; RV32IF-NEXT: addi sp, sp, 16 552; RV32IF-NEXT: ret 553; 554; RV64IF-LABEL: nearbyint_f32: 555; RV64IF: # %bb.0: 556; RV64IF-NEXT: addi sp, sp, -16 557; RV64IF-NEXT: sd ra, 8(sp) 558; RV64IF-NEXT: call nearbyintf 559; RV64IF-NEXT: ld ra, 8(sp) 560; RV64IF-NEXT: addi sp, sp, 16 561; RV64IF-NEXT: ret 562 %1 = call float @llvm.nearbyint.f32(float %a) 563 ret float %1 564} 565 566declare float @llvm.round.f32(float) 567 568define float @round_f32(float %a) nounwind { 569; RV32IF-LABEL: round_f32: 570; RV32IF: # %bb.0: 571; RV32IF-NEXT: addi sp, sp, -16 572; RV32IF-NEXT: sw ra, 12(sp) 573; RV32IF-NEXT: call roundf 574; RV32IF-NEXT: lw ra, 12(sp) 575; RV32IF-NEXT: addi sp, sp, 16 576; RV32IF-NEXT: ret 577; 578; RV64IF-LABEL: round_f32: 579; RV64IF: # %bb.0: 580; RV64IF-NEXT: addi sp, sp, -16 581; RV64IF-NEXT: sd ra, 8(sp) 582; RV64IF-NEXT: call roundf 583; RV64IF-NEXT: ld ra, 8(sp) 584; RV64IF-NEXT: addi sp, sp, 16 585; RV64IF-NEXT: ret 586 %1 = call float @llvm.round.f32(float %a) 587 ret float %1 588} 589