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Searched refs:FSUB_D (Results 1 – 17 of 17) sorted by relevance

/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
Dfloating_point_vec_arithmetic_operations.mir125 ; P5600: [[FSUB_D:%[0-9]+]]:msa128d = FSUB_D [[LD_D]], [[LD_D1]]
126 ; P5600: ST_D [[FSUB_D]], [[COPY2]], 0 :: (store 16 into %ir.c)
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrInfoD.td101 def FSUB_D : FPALUD_rr_frm<0b0000101, "fsub.d">;
102 def : FPALUDDynFrmAlias<FSUB_D, "fsub.d">;
246 def : PatFpr64Fpr64DynFrm<fsub, FSUB_D>;
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfoD.td100 def FSUB_D : FPALUD_rr_frm<0b0000101, "fsub.d">,
102 def : FPALUDDynFrmAlias<FSUB_D, "fsub.d">;
253 def : PatFpr64Fpr64DynFrm<fsub, FSUB_D>;
/external/mesa3d/src/mesa/x86/
Dassyntax.h781 #define FSUB_D(a) CHOICE(fsubl a, fsubl a, fsubd a) macro
1494 #define FSUB_D(a) fsub D_(a) macro
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc829 134236223U, // FSUB_D
2618 0U, // FSUB_D
DMipsGenDisassemblerTables.inc2864 /* 9544 */ MCD_OPC_Decode, 172, 6, 140, 1, // Opcode: FSUB_D
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenMCCodeEmitter.inc1618 UINT64_C(2019557403), // FSUB_D
8697 case Mips::FSUB_D:
11080 CEFBS_HasStdEnc_HasMSA, // FSUB_D = 1605
DMipsGenAsmWriter.inc2846 268454183U, // FSUB_D
5600 0U, // FSUB_D
DMipsGenFastISel.inc1673 return fastEmitInst_rr(Mips::FSUB_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
DMipsGenInstrInfo.inc1620 FSUB_D = 1605,
6466 …5, 3, 1, 4, 656, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1605 = FSUB_D
DMipsGenDisassemblerTables.inc5186 /* 11824 */ MCD::OPC_Decode, 197, 12, 128, 2, // Opcode: FSUB_D
DMipsGenAsmMatcher.inc6675 …{ 4785 /* fsub.d */, Mips::FSUB_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMF…
DMipsGenGlobalISel.inc22064 …4] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUB_D:{ *:[v2f64] } MSA1…
22065 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D,
DMipsGenDAGISel.inc27093 /* 51254*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSUB_D), 0,
27096 … // Dst: (FSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td3112 def FSUB_D : FSUB_D_ENC, FSUB_D_DESC;
/external/llvm-project/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td3158 def FSUB_D : FSUB_D_ENC, FSUB_D_DESC;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td3138 def FSUB_D : FSUB_D_ENC, FSUB_D_DESC;