| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86CmovConversion.cpp | 715 Register FalseReg = in convertCmovInstsToBranches() local
719 auto FRIt = FalseBBRegRewriteTable.find(FalseReg); in convertCmovInstsToBranches()
722 FalseReg = FRIt->second; in convertCmovInstsToBranches()
724 FalseBBRegRewriteTable[MI.getOperand(0).getReg()] = FalseReg; in convertCmovInstsToBranches()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86CmovConversion.cpp | 715 Register FalseReg = in convertCmovInstsToBranches() local
719 auto FRIt = FalseBBRegRewriteTable.find(FalseReg); in convertCmovInstsToBranches()
722 FalseReg = FRIt->second; in convertCmovInstsToBranches()
724 FalseBBRegRewriteTable[MI.getOperand(0).getReg()] = FalseReg; in convertCmovInstsToBranches()
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.cpp | 509 MachineOperand FalseReg = MI.getOperand(Invert ? 1 : 2); in optimizeSelect() local
511 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg()); in optimizeSelect()
535 FalseReg.setImplicit(); in optimizeSelect()
536 NewMI.addOperand(FalseReg); in optimizeSelect()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.cpp | 506 MachineOperand FalseReg = MI.getOperand(Invert ? 1 : 2); in optimizeSelect() local
508 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg()); in optimizeSelect()
532 FalseReg.setImplicit(); in optimizeSelect()
533 NewMI.add(FalseReg); in optimizeSelect()
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| /external/llvm-project/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.cpp | 506 MachineOperand FalseReg = MI.getOperand(Invert ? 1 : 2); in optimizeSelect() local
508 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg()); in optimizeSelect()
532 FalseReg.setImplicit(); in optimizeSelect()
533 NewMI.add(FalseReg); in optimizeSelect()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 757 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
770 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
796 unsigned FalseReg) const { in insertSelect()
803 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in insertSelect()
855 unsigned FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect()
856 SecondReg = SwapOps ? TrueReg : FalseReg; in insertSelect()
2224 unsigned TrueReg, unsigned FalseReg, in selectReg() argument
2231 return Imm1 < Imm2 ? TrueReg : FalseReg; in selectReg()
2233 return Imm1 > Imm2 ? TrueReg : FalseReg; in selectReg()
2235 return Imm1 == Imm2 ? TrueReg : FalseReg; in selectReg()
[all …]
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.h | 182 unsigned FalseReg) const override;
|
| D | PPCInstrInfo.cpp | 687 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
703 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
729 unsigned FalseReg) const { in insertSelect()
739 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in insertSelect()
791 unsigned FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect()
792 SecondReg = SwapOps ? TrueReg : FalseReg; in insertSelect()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.h | 159 unsigned FalseReg) const override;
|
| D | AArch64InstrInfo.cpp | 368 unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, in canInsertSelect() argument
373 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
389 else if (canFoldIntoCSel(MRI, FalseReg)) in canInsertSelect()
411 unsigned TrueReg, unsigned FalseReg) const { in insertSelect()
519 TrueReg = FalseReg; in insertSelect()
521 FoldedOpc = canFoldIntoCSel(MRI, FalseReg, &NewVReg); in insertSelect()
525 FalseReg = NewVReg; in insertSelect()
534 MRI.constrainRegClass(FalseReg, RC); in insertSelect()
537 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(TrueReg).addReg(FalseReg).addImm( in insertSelect()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyFastISel.cpp | 728 unsigned FalseReg = getRegForValue(Select->getFalseValue()); in selectSelect() local
729 if (FalseReg == 0) in selectSelect()
733 std::swap(TrueReg, FalseReg); in selectSelect()
764 .addReg(FalseReg) in selectSelect()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.cpp | 535 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
547 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
571 unsigned FalseReg) const { in insertSelect()
591 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg); in insertSelect()
593 FalseReg = FReg; in insertSelect()
604 .addReg(FalseReg).addReg(TrueReg) in insertSelect()
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| D | SystemZInstrInfo.h | 229 unsigned FalseReg) const override;
|
| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 1099 Register FalseReg, int &CondCycles, in canInsertSelect() argument
1112 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
1138 Register FalseReg) const { in insertSelect()
1145 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in insertSelect()
1197 Register FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect()
1198 SecondReg = SwapOps ? TrueReg : FalseReg; in insertSelect()
2664 unsigned TrueReg, unsigned FalseReg, in selectReg() argument
2671 return Imm1 < Imm2 ? TrueReg : FalseReg; in selectReg()
2673 return Imm1 > Imm2 ? TrueReg : FalseReg; in selectReg()
2675 return Imm1 == Imm2 ? TrueReg : FalseReg; in selectReg()
[all …]
|
| /external/llvm-project/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.h | 244 Register FalseReg) const override;
|
| D | SystemZInstrInfo.cpp | 536 Register FalseReg, int &CondCycles, in canInsertSelect() argument
548 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
572 Register FalseReg) const { in insertSelect()
592 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg); in insertSelect()
594 FalseReg = FReg; in insertSelect()
605 .addReg(FalseReg).addReg(TrueReg) in insertSelect()
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 690 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
714 unsigned TrueReg, unsigned FalseReg) const { in insertSelect() argument
|
| /external/llvm-project/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyFastISel.cpp | 906 unsigned FalseReg = getRegForValue(Select->getFalseValue()); in selectSelect() local
907 if (FalseReg == 0) in selectSelect()
911 std::swap(TrueReg, FalseReg); in selectSelect()
954 .addReg(FalseReg) in selectSelect()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyFastISel.cpp | 899 unsigned FalseReg = getRegForValue(Select->getFalseValue()); in selectSelect() local
900 if (FalseReg == 0) in selectSelect()
904 std::swap(TrueReg, FalseReg); in selectSelect()
939 .addReg(FalseReg) in selectSelect()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.h | 297 unsigned TrueReg, unsigned FalseReg,
304 unsigned TrueReg, unsigned FalseReg) const override;
309 unsigned TrueReg, unsigned FalseReg) const;
|
| D | SIInstrInfo.cpp | 824 unsigned FalseReg) const { in insertVectorSelect()
839 .addReg(FalseReg) in insertVectorSelect()
854 .addReg(FalseReg) in insertVectorSelect()
868 .addReg(FalseReg) in insertVectorSelect()
882 .addReg(FalseReg) in insertVectorSelect()
898 .addReg(FalseReg) in insertVectorSelect()
914 .addReg(FalseReg) in insertVectorSelect()
932 .addReg(FalseReg) in insertVectorSelect()
2128 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
2136 assert(MRI.getRegClass(FalseReg) == RC); in canInsertSelect()
[all …]
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 788 auto FalseReg = MIB.getReg(3); in selectSelect() local
790 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) && in selectSelect()
795 .addUse(FalseReg) in selectSelect()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.h | 304 Register TrueReg, Register FalseReg, int &CondCycles,
310 Register TrueReg, Register FalseReg) const override;
315 Register TrueReg, Register FalseReg) const;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.h | 198 unsigned FalseReg) const override;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 790 auto FalseReg = MIB->getOperand(3).getReg(); in selectSelect() local
792 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) && in selectSelect()
797 .addUse(FalseReg) in selectSelect()
|