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Searched refs:FirstReg (Results 1 – 25 of 35) sorted by relevance

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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DFunctionLoweringInfo.cpp375 unsigned FirstReg = 0; in CreateRegs() local
383 if (!FirstReg) FirstReg = R; in CreateRegs()
386 return FirstReg; in CreateRegs()
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DFunctionLoweringInfo.cpp386 Register FirstReg; in CreateRegs() local
394 if (!FirstReg) FirstReg = R; in CreateRegs()
397 return FirstReg; in CreateRegs()
/external/llvm/lib/CodeGen/SelectionDAG/
DFunctionLoweringInfo.cpp382 unsigned FirstReg = 0; in CreateRegs() local
390 if (!FirstReg) FirstReg = R; in CreateRegs()
393 return FirstReg; in CreateRegs()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DAggressiveAntiDepBreaker.cpp505 unsigned FirstReg = 0; in ScanInstruction() local
512 if (FirstReg != 0) { in ScanInstruction()
514 State->UnionGroups(FirstReg, Reg); in ScanInstruction()
517 FirstReg = Reg; in ScanInstruction()
521 LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n'); in ScanInstruction()
/external/llvm/lib/CodeGen/
DAggressiveAntiDepBreaker.cpp487 unsigned FirstReg = 0; in ScanInstruction() local
494 if (FirstReg != 0) { in ScanInstruction()
496 State->UnionGroups(FirstReg, Reg); in ScanInstruction()
499 FirstReg = Reg; in ScanInstruction()
503 DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n'); in ScanInstruction()
/external/llvm-project/llvm/lib/CodeGen/
DAggressiveAntiDepBreaker.cpp500 unsigned FirstReg = 0; in ScanInstruction() local
507 if (FirstReg != 0) { in ScanInstruction()
509 State->UnionGroups(FirstReg, Reg); in ScanInstruction()
512 FirstReg = Reg; in ScanInstruction()
516 LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n'); in ScanInstruction()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp2149 unsigned &FirstReg, in CanFormLdStDWord() argument
2212 FirstReg = Op0->getOperand(0).getReg(); in CanFormLdStDWord()
2214 if (FirstReg == SecondReg) in CanFormLdStDWord()
2316 unsigned FirstReg = 0, SecondReg = 0; in RescheduleOps() local
2324 FirstReg, SecondReg, BaseReg, in RescheduleOps()
2331 MRI->constrainRegClass(FirstReg, TRC); in RescheduleOps()
2337 .addReg(FirstReg, RegState::Define) in RescheduleOps()
2351 .addReg(FirstReg) in RescheduleOps()
2369 MRI->setRegAllocationHint(FirstReg, ARMRI::RegPairEven, SecondReg); in RescheduleOps()
2370 MRI->setRegAllocationHint(SecondReg, ARMRI::RegPairOdd, FirstReg); in RescheduleOps()
/external/llvm/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp2057 unsigned &FirstReg, in CanFormLdStDWord() argument
2119 FirstReg = Op0->getOperand(0).getReg(); in CanFormLdStDWord()
2121 if (FirstReg == SecondReg) in CanFormLdStDWord()
2217 unsigned FirstReg = 0, SecondReg = 0; in RescheduleOps() local
2225 FirstReg, SecondReg, BaseReg, in RescheduleOps()
2232 MRI->constrainRegClass(FirstReg, TRC); in RescheduleOps()
2238 .addReg(FirstReg, RegState::Define) in RescheduleOps()
2252 .addReg(FirstReg) in RescheduleOps()
2270 MRI->setRegAllocationHint(FirstReg, ARMRI::RegPairEven, SecondReg); in RescheduleOps()
2271 MRI->setRegAllocationHint(SecondReg, ARMRI::RegPairOdd, FirstReg); in RescheduleOps()
/external/llvm-project/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp3365 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadSingleImmToGPR() local
3370 return loadImmediate(ImmOp32, FirstReg, Mips::NoRegister, true, false, IDLoc, in expandLoadSingleImmToGPR()
3382 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadSingleImmToFPR() local
3400 TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI); in expandLoadSingleImmToFPR()
3423 TOut.emitRRX(Mips::LWC1, FirstReg, TmpReg, MCOperand::createExpr(LoExpr), in expandLoadSingleImmToFPR()
3436 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadDoubleImmToGPR() local
3443 if (loadImmediate(ImmOp64, FirstReg, Mips::NoRegister, false, false, in expandLoadDoubleImmToGPR()
3447 if (loadImmediate(Hi_32(ImmOp64), FirstReg, Mips::NoRegister, true, false, in expandLoadDoubleImmToGPR()
3451 if (loadImmediate(0, nextReg(FirstReg), Mips::NoRegister, true, false, in expandLoadDoubleImmToGPR()
3485 TOut.emitRRI(Mips::LD, FirstReg, TmpReg, 0, IDLoc, STI); in expandLoadDoubleImmToGPR()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp3337 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadSingleImmToGPR() local
3342 return loadImmediate(ImmOp32, FirstReg, Mips::NoRegister, true, false, IDLoc, in expandLoadSingleImmToGPR()
3354 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadSingleImmToFPR() local
3372 TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI); in expandLoadSingleImmToFPR()
3395 TOut.emitRRX(Mips::LWC1, FirstReg, TmpReg, MCOperand::createExpr(LoExpr), in expandLoadSingleImmToFPR()
3408 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadDoubleImmToGPR() local
3415 if (loadImmediate(ImmOp64, FirstReg, Mips::NoRegister, false, false, in expandLoadDoubleImmToGPR()
3419 if (loadImmediate(Hi_32(ImmOp64), FirstReg, Mips::NoRegister, true, false, in expandLoadDoubleImmToGPR()
3423 if (loadImmediate(0, nextReg(FirstReg), Mips::NoRegister, true, false, in expandLoadDoubleImmToGPR()
3457 TOut.emitRRI(Mips::LD, FirstReg, TmpReg, 0, IDLoc, STI); in expandLoadDoubleImmToGPR()
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp791 unsigned FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect() local
797 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) || in insertSelect()
798 MRI.getRegClass(FirstReg)->contains(PPC::X0)) { in insertSelect()
800 MRI.getRegClass(FirstReg)->contains(PPC::X0) ? in insertSelect()
802 unsigned OldFirstReg = FirstReg; in insertSelect()
803 FirstReg = MRI.createVirtualRegister(FirstRC); in insertSelect()
804 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg) in insertSelect()
809 .addReg(FirstReg).addReg(SecondReg) in insertSelect()
/external/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp1202 unsigned FirstReg = FirstRegs[NumRegs - 1]; in addVectorList64Operands() local
1205 MCOperand::createReg(FirstReg + getVectorListStart() - AArch64::Q0)); in addVectorList64Operands()
1215 unsigned FirstReg = FirstRegs[NumRegs - 1]; in addVectorList128Operands() local
1218 MCOperand::createReg(FirstReg + getVectorListStart() - AArch64::Q0)); in addVectorList128Operands()
2979 int64_t FirstReg = tryMatchVectorRegister(Kind, true); in parseVectorList() local
2980 if (FirstReg == -1) in parseVectorList()
2982 int64_t PrevReg = FirstReg; in parseVectorList()
3041 FirstReg, Count, NumElements, ElementKind, S, getLoc(), getContext())); in parseVectorList()
4616 int FirstReg = tryParseRegister(); in tryParseGPRSeqPair() local
4617 if (FirstReg == -1) { in tryParseGPRSeqPair()
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp2207 Register &FirstReg, Register &SecondReg, Register &BaseReg, int &Offset, in CanFormLdStDWord() argument
2266 FirstReg = Op0->getOperand(0).getReg(); in CanFormLdStDWord()
2268 if (FirstReg == SecondReg) in CanFormLdStDWord()
2370 Register FirstReg, SecondReg; in RescheduleOps() local
2378 FirstReg, SecondReg, BaseReg, in RescheduleOps()
2385 MRI->constrainRegClass(FirstReg, TRC); in RescheduleOps()
2391 .addReg(FirstReg, RegState::Define) in RescheduleOps()
2405 .addReg(FirstReg) in RescheduleOps()
2423 MRI->setRegAllocationHint(FirstReg, ARMRI::RegPairEven, SecondReg); in RescheduleOps()
2424 MRI->setRegAllocationHint(SecondReg, ARMRI::RegPairOdd, FirstReg); in RescheduleOps()
/external/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64InstPrinter.cpp1296 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) in printVectorList() local
1297 Reg = FirstReg; in printVectorList()
1298 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) in printVectorList() local
1299 Reg = FirstReg; in printVectorList()
1300 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0)) in printVectorList() local
1301 Reg = FirstReg; in printVectorList()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64InstPrinter.cpp1282 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) in printVectorList() local
1283 Reg = FirstReg; in printVectorList()
1284 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) in printVectorList() local
1285 Reg = FirstReg; in printVectorList()
1286 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0)) in printVectorList() local
1287 Reg = FirstReg; in printVectorList()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp3724 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, in copyByValRegs() argument
3729 unsigned NumRegs = LastReg - FirstReg; in copyByValRegs()
3738 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes); in copyByValRegs()
3756 unsigned ArgReg = ByValArgRegs[FirstReg + I]; in copyByValRegs()
3773 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, in passByValArg() argument
3782 unsigned NumRegs = LastReg - FirstReg; in passByValArg()
3797 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
3847 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
3922 unsigned FirstReg = 0; in HandleByVal() local
3938 FirstReg = State->getFirstUnallocated(IntArgRegs); in HandleByVal()
[all …]
DMipsISelLowering.h468 const Argument *FuncArg, unsigned FirstReg,
477 unsigned FirstReg, unsigned LastReg,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsISelLowering.cpp4307 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, in copyByValRegs() argument
4312 unsigned NumRegs = LastReg - FirstReg; in copyByValRegs()
4321 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes); in copyByValRegs()
4344 unsigned ArgReg = ByValArgRegs[FirstReg + I]; in copyByValRegs()
4360 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, in passByValArg() argument
4369 unsigned NumRegs = LastReg - FirstReg; in passByValArg()
4383 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
4432 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
4507 unsigned FirstReg = 0; in HandleByVal() local
4523 FirstReg = State->getFirstUnallocated(IntArgRegs); in HandleByVal()
[all …]
DMipsISelLowering.h581 const Argument *FuncArg, unsigned FirstReg,
590 unsigned FirstReg, unsigned LastReg,
/external/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.cpp1307 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) in printVectorList() local
1308 Reg = FirstReg; in printVectorList()
1309 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) in printVectorList() local
1310 Reg = FirstReg; in printVectorList()
/external/llvm-project/llvm/lib/Target/Mips/
DMipsISelLowering.cpp4321 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, in copyByValRegs() argument
4326 unsigned NumRegs = LastReg - FirstReg; in copyByValRegs()
4335 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes); in copyByValRegs()
4358 unsigned ArgReg = ByValArgRegs[FirstReg + I]; in copyByValRegs()
4374 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, in passByValArg() argument
4384 unsigned NumRegs = LastReg - FirstReg; in passByValArg()
4398 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
4447 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
4521 unsigned FirstReg = 0; in HandleByVal() local
4537 FirstReg = State->getFirstUnallocated(IntArgRegs); in HandleByVal()
[all …]
DMipsISelLowering.h567 const Argument *FuncArg, unsigned FirstReg,
576 unsigned FirstReg, unsigned LastReg,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp1512 unsigned FirstReg = FirstRegs[(unsigned)RegTy][NumRegs]; in addVectorListOperands() local
1513 Inst.addOperand(MCOperand::createReg(FirstReg + getVectorListStart() - in addVectorListOperands()
3343 unsigned FirstReg; in tryParseVectorList() local
3344 auto ParseRes = ParseVector(FirstReg, Kind, getLoc(), ExpectMatch); in tryParseVectorList()
3354 int64_t PrevReg = FirstReg; in tryParseVectorList()
3424 FirstReg, Count, NumElements, ElementWidth, VectorKind, S, getLoc(), in tryParseVectorList()
5604 unsigned FirstReg; in tryParseGPRSeqPair() local
5605 OperandMatchResultTy Res = tryParseScalarRegister(FirstReg); in tryParseGPRSeqPair()
5614 bool isXReg = XRegClass.contains(FirstReg), in tryParseGPRSeqPair()
5615 isWReg = WRegClass.contains(FirstReg); in tryParseGPRSeqPair()
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp1553 unsigned FirstReg = FirstRegs[(unsigned)RegTy][NumRegs]; in addVectorListOperands() local
1554 Inst.addOperand(MCOperand::createReg(FirstReg + getVectorListStart() - in addVectorListOperands()
3398 unsigned FirstReg; in tryParseVectorList() local
3399 auto ParseRes = ParseVector(FirstReg, Kind, getLoc(), ExpectMatch); in tryParseVectorList()
3409 int64_t PrevReg = FirstReg; in tryParseVectorList()
3479 FirstReg, Count, NumElements, ElementWidth, VectorKind, S, getLoc(), in tryParseVectorList()
6044 unsigned FirstReg; in tryParseGPRSeqPair() local
6045 OperandMatchResultTy Res = tryParseScalarRegister(FirstReg); in tryParseGPRSeqPair()
6054 bool isXReg = XRegClass.contains(FirstReg), in tryParseGPRSeqPair()
6055 isWReg = WRegClass.contains(FirstReg); in tryParseGPRSeqPair()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp855 unsigned FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect() local
861 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) || in insertSelect()
862 MRI.getRegClass(FirstReg)->contains(PPC::X0)) { in insertSelect()
864 MRI.getRegClass(FirstReg)->contains(PPC::X0) ? in insertSelect()
866 unsigned OldFirstReg = FirstReg; in insertSelect()
867 FirstReg = MRI.createVirtualRegister(FirstRC); in insertSelect()
868 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg) in insertSelect()
873 .addReg(FirstReg).addReg(SecondReg) in insertSelect()

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