| /external/igt-gpu-tools/assembler/ |
| D | gram.y | 45 #define GEN8(i) (&(i)->insn.gen8) macro
264 return gen8_access_mode(GEN8(insn)); in access_mode()
272 return gen8_exec_size(GEN8(insn)); in exec_size()
280 gen8_set_exec_size(GEN8(insn), execsize); in set_execsize()
956 … gen8_set_thread_control(GEN8(&$$), gen8_thread_control(GEN8(&$$)) | BRW_THREAD_SWITCH);
971 … gen8_set_thread_control(GEN8(&$$), gen8_thread_control(GEN8(&$$)) | BRW_THREAD_SWITCH);
1194 gen8_set_src1_reg_file(GEN8(&$$), BRW_IMMEDIATE_VALUE);
1195 gen8_set_src1_reg_type(GEN8(&$$), BRW_REGISTER_TYPE_D);
1196 gen9_set_send_extdesc(GEN8(&$$), 0);
1198 gen8_set_src1_reg_file(GEN8(&$$), BRW_IMMEDIATE_VALUE);
[all …]
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| /external/igt-gpu-tools/tests/i915/ |
| D | gem_ctx_isolation.c | 54 #define GEN8 (ALL << 8) macro
93 { "GPUGPU_DISPATCHDIMX", GEN8, RCS0, 0x2500 },
94 { "GPUGPU_DISPATCHDIMY", GEN8, RCS0, 0x2504 },
95 { "GPUGPU_DISPATCHDIMZ", GEN8, RCS0, 0x2508 },
96 { "MI_PREDICATE_SRC0", GEN8, RCS0, 0x2400, 2 },
97 { "MI_PREDICATE_SRC1", GEN8, RCS0, 0x2408, 2 },
98 { "MI_PREDICATE_DATA", GEN8, RCS0, 0x2410, 2 },
99 { "MI_PRED_RESULT", GEN8, RCS0, 0x2418, .write_mask = 0x1 },
106 { "GPGPU_THREADS_DISPATCHED", GEN8, RCS0, 0x2290, 2 },
107 { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2, .write_mask = ~0x3 },
[all …]
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| /external/mesa3d/src/intel/compiler/ |
| D | brw_gen_enum.h | 34 GEN8 = (1 << 6), enumerator
54 case 8: return GEN8; in gen_from_devinfo()
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| D | brw_eu.cpp | 614 { BRW_OPCODE_SMOV, 10, "smov", 0, 0, GEN_GE(GEN8) & GEN_LT(GEN12) },
626 { BRW_OPCODE_CSEL, 18, "csel", 3, 1, GEN_GE(GEN8) & GEN_LT(GEN12) },
658 { BRW_OPCODE_GOTO, 46, "goto", 0, 0, GEN_GE(GEN8) },
694 { BRW_OPCODE_MADM, 93, "madm", 3, 1, GEN_GE(GEN8) },
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| /external/skqp/src/compute/hs/ |
| D | README.md | 69 Intel | GEN8+ | :white_check_mark: | :white_check_mark: | :x: …
171 Intel | GEN8+ | :white_check_mark: | :white_check_mark: | :x: …
184 be compatible with all GEN8+ devices and drivers.
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| /external/skqp/src/compute/hs/vk/intel/gen8/u64/ |
| D | gen.bat | 31 :: This should be the proper mapping onto the Intel GEN8+ subslices but the compiler is spilling
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| /external/skqp/src/compute/hs/vk/intel/gen8/u32/ |
| D | gen.bat | 34 :: This should be the proper mapping onto the Intel GEN8+ subslices but the compiler is spilling
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| /external/skqp/src/compute/hs/cl/intel/gen8/u32/ |
| D | gen.bat | 17 :: This should be the proper mapping onto the Intel GEN8+ subslices but the compiler is spilling
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| /external/skqp/src/compute/hs/cl/intel/gen8/u64/ |
| D | gen.bat | 14 :: This should be the proper mapping onto the Intel GEN8+ subslices but the compiler is spilling
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| /external/mesa3d/docs/relnotes/ |
| D | 17.0.4.rst | 43 - [GEN8+] piglit.spec.arb_stencil_texturing.glblitframebuffer
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| D | 11.1.2.rst | 106 - i965/vec4: Use UW type for multiply into accumulator on GEN8+
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| D | 18.3.0.rst | 121 - [GEN8+] Hang when discarding a fragment if dual source blending is
156 - [GEN8+] up to 10% perf drop on several 3D benchmarks
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| D | 12.0.0.rst | 205 [GEN8] Ungine Valley fails to run due to "intel_do_flush_locked
250 [ES3.1CTS,GEN8]
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| D | 17.1.0.rst | 203 - [GEN8+] piglit.spec.arb_stencil_texturing.glblitframebuffer
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| D | 18.2.0.rst | 288 - [GEN8+] up to 10% perf drop on several 3D benchmarks
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| D | 19.0.0.rst | 72 - [GEN8+] up to 10% perf drop on several 3D benchmarks
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| D | 19.1.0.rst | 83 - [GEN8+] up to 10% perf drop on several 3D benchmarks
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| /external/skqp/src/compute/skc/platforms/cl_12/kernels/ |
| D | render.cl | 1731 // Confirmed: GEN8 has 4KB SLM workgroup min while GEN9 is 1KB.
|