| /external/llvm-project/clang/lib/CodeGen/ |
| D | CodeGenTypeCache.h | 39 llvm::Type *HalfTy, *BFloatTy, *FloatTy, *DoubleTy; member
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| D | CGBuiltin.cpp | 5054 return llvm::FixedVectorType::get(CGF->HalfTy, V1Ty ? 1 : (4 << IsQuad)); in GetNeonType()
5080 return llvm::FixedVectorType::get(CGF->HalfTy, (4 << IsQuad)); in GetFloatNeonType()
6172 Ty = HalfTy; in EmitCommonNeonBuiltinExpr()
6666 llvm::FixedVectorType::get(HalfTy, Ty->getPrimitiveSizeInBits() / 16); in EmitCommonNeonBuiltinExpr()
6673 llvm::FixedVectorType::get(HalfTy, Ty->getPrimitiveSizeInBits() / 16); in EmitCommonNeonBuiltinExpr()
6680 llvm::FixedVectorType::get(HalfTy, Ty->getPrimitiveSizeInBits() / 16); in EmitCommonNeonBuiltinExpr()
6687 llvm::FixedVectorType::get(HalfTy, Ty->getPrimitiveSizeInBits() / 16); in EmitCommonNeonBuiltinExpr()
9321 return EmitNeonCall(CGM.getIntrinsic(Intrinsic::fabs, HalfTy), Ops, "vabs"); in EmitAArch64BuiltinExpr()
9358 llvm::Type *FTy = HalfTy; in EmitAArch64BuiltinExpr()
9383 llvm::Type* FTy = HalfTy; in EmitAArch64BuiltinExpr()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 3086 const LLT HalfTy, const LLT AmtTy) { in narrowScalarShiftByConstant() argument
3088 Register InL = MRI.createGenericVirtualRegister(HalfTy); in narrowScalarShiftByConstant()
3089 Register InH = MRI.createGenericVirtualRegister(HalfTy); in narrowScalarShiftByConstant()
3098 LLT NVT = HalfTy; in narrowScalarShiftByConstant()
3099 unsigned NVTBits = HalfTy.getSizeInBits(); in narrowScalarShiftByConstant()
3198 const LLT HalfTy = LLT::scalar(NewBitSize); in narrowScalarShift() local
3204 MI, KShiftAmt->getOperand(1).getCImm()->getValue(), HalfTy, ShiftAmtTy); in narrowScalarShift()
3212 Register InL = MRI.createGenericVirtualRegister(HalfTy); in narrowScalarShift()
3213 Register InH = MRI.createGenericVirtualRegister(HalfTy); in narrowScalarShift()
3227 auto LoS = MIRBuilder.buildShl(HalfTy, InL, Amt); in narrowScalarShift()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPURegisterBankInfo.cpp | 678 LLT HalfTy, in split64BitValueForMapping() argument
680 assert(HalfTy.getSizeInBits() == 32); in split64BitValueForMapping()
682 Register LoLHS = MRI->createGenericVirtualRegister(HalfTy); in split64BitValueForMapping()
683 Register HiLHS = MRI->createGenericVirtualRegister(HalfTy); in split64BitValueForMapping()
1587 LLT HalfTy = getHalfSizedType(DstTy); in applyMappingImpl() local
1600 split64BitValueForMapping(B, Src1Regs, HalfTy, MI.getOperand(2).getReg()); in applyMappingImpl()
1602 setRegsToType(MRI, Src1Regs, HalfTy); in applyMappingImpl()
1606 split64BitValueForMapping(B, Src2Regs, HalfTy, MI.getOperand(3).getReg()); in applyMappingImpl()
1608 setRegsToType(MRI, Src2Regs, HalfTy); in applyMappingImpl()
1610 setRegsToType(MRI, DefRegs, HalfTy); in applyMappingImpl()
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| D | AMDGPURegisterBankInfo.h | 120 LLT HalfTy,
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| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 4072 const LLT HalfTy, const LLT AmtTy) { in narrowScalarShiftByConstant() argument
4074 Register InL = MRI.createGenericVirtualRegister(HalfTy); in narrowScalarShiftByConstant()
4075 Register InH = MRI.createGenericVirtualRegister(HalfTy); in narrowScalarShiftByConstant()
4084 LLT NVT = HalfTy; in narrowScalarShiftByConstant()
4085 unsigned NVTBits = HalfTy.getSizeInBits(); in narrowScalarShiftByConstant()
4184 const LLT HalfTy = LLT::scalar(NewBitSize); in narrowScalarShift() local
4190 MI, KShiftAmt->getOperand(1).getCImm()->getValue(), HalfTy, ShiftAmtTy); in narrowScalarShift()
4198 Register InL = MRI.createGenericVirtualRegister(HalfTy); in narrowScalarShift()
4199 Register InH = MRI.createGenericVirtualRegister(HalfTy); in narrowScalarShift()
4213 auto LoS = MIRBuilder.buildShl(HalfTy, InL, Amt); in narrowScalarShift()
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| D | CombinerHelper.cpp | 2042 LLT HalfTy = LLT::scalar(HalfSize); in applyCombineShiftToUnmerge() local
2045 auto Unmerge = Builder.buildUnmerge(HalfTy, SrcReg); in applyCombineShiftToUnmerge()
2057 Narrowed = Builder.buildLShr(HalfTy, Narrowed, in applyCombineShiftToUnmerge()
2058 Builder.buildConstant(HalfTy, NarrowShiftAmt)).getReg(0); in applyCombineShiftToUnmerge()
2061 auto Zero = Builder.buildConstant(HalfTy, 0); in applyCombineShiftToUnmerge()
2070 Narrowed = Builder.buildShl(HalfTy, Narrowed, in applyCombineShiftToUnmerge()
2071 Builder.buildConstant(HalfTy, NarrowShiftAmt)).getReg(0); in applyCombineShiftToUnmerge()
2074 auto Zero = Builder.buildConstant(HalfTy, 0); in applyCombineShiftToUnmerge()
2079 HalfTy, Unmerge.getReg(1), in applyCombineShiftToUnmerge()
2080 Builder.buildConstant(HalfTy, HalfSize - 1)); in applyCombineShiftToUnmerge()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLoweringHVX.cpp | 231 MVT HalfTy = MVT::getVectorVT(VecTy.getVectorElementType(), NumElem/2); in typeSplit() local
232 return { HalfTy, HalfTy }; in typeSplit()
1111 MVT HalfTy = typeSplit(VecTy).first; in LowerHvxConcatVectors() local
1112 SDValue V0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfTy, in LowerHvxConcatVectors()
1114 SDValue V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfTy, in LowerHvxConcatVectors()
1474 MVT HalfTy = typeSplit(ResTy).first; in SplitHvxPairOp() local
1475 SDValue L = DAG.getNode(Op.getOpcode(), dl, HalfTy, OpsL); in SplitHvxPairOp()
1476 SDValue H = DAG.getNode(Op.getOpcode(), dl, HalfTy, OpsH); in SplitHvxPairOp()
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| D | HexagonISelDAGToDAGHVX.cpp | 1012 MVT HalfTy = MVT::getVectorVT(OpTy.getVectorElementType(), in materialize() local
1016 Op = DAG.getTargetExtractSubreg(Sub, dl, HalfTy, Op); in materialize()
1168 MVT HalfTy = getSingleVT(MVT::i8); in packp() local
1171 OpRef Out[2] = { OpRef::undef(HalfTy), OpRef::undef(HalfTy) }; in packp()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPURegisterBankInfo.h | 129 LLT HalfTy,
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| D | AMDGPURegisterBankInfo.cpp | 663 LLT HalfTy, in split64BitValueForMapping() argument
665 assert(HalfTy.getSizeInBits() == 32); in split64BitValueForMapping()
667 Register LoLHS = MRI->createGenericVirtualRegister(HalfTy); in split64BitValueForMapping()
668 Register HiLHS = MRI->createGenericVirtualRegister(HalfTy); in split64BitValueForMapping()
2231 LLT HalfTy = getHalfSizedType(DstTy); in applyMappingImpl() local
2244 split64BitValueForMapping(B, Src1Regs, HalfTy, MI.getOperand(2).getReg()); in applyMappingImpl()
2246 setRegsToType(MRI, Src1Regs, HalfTy); in applyMappingImpl()
2250 split64BitValueForMapping(B, Src2Regs, HalfTy, MI.getOperand(3).getReg()); in applyMappingImpl()
2252 setRegsToType(MRI, Src2Regs, HalfTy); in applyMappingImpl()
2254 setRegsToType(MRI, DefRegs, HalfTy); in applyMappingImpl()
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| /external/llvm/lib/IR/ |
| D | LLVMContextImpl.cpp | 28 HalfTy(C, Type::HalfTyID), in LLVMContextImpl()
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| D | Type.cpp | 156 Type *Type::getHalfTy(LLVMContext &C) { return &C.pImpl->HalfTy; } in getHalfTy()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/IR/ |
| D | LLVMContextImpl.cpp | 27 HalfTy(C, Type::HalfTyID), in LLVMContextImpl()
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| D | Type.cpp | 167 Type *Type::getHalfTy(LLVMContext &C) { return &C.pImpl->HalfTy; } in getHalfTy()
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| /external/llvm-project/llvm/lib/IR/ |
| D | LLVMContextImpl.cpp | 28 HalfTy(C, Type::HalfTyID), in LLVMContextImpl()
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| D | Type.cpp | 172 Type *Type::getHalfTy(LLVMContext &C) { return &C.pImpl->HalfTy; } in getHalfTy()
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| /external/llvm-project/clang/include/clang/AST/ |
| D | BuiltinTypes.def | 201 FLOATING_TYPE(Half, HalfTy)
213 FLOATING_TYPE(Float16, HalfTy)
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | LegalizerHelper.h | 214 LLT HalfTy, LLT ShiftAmtTy);
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLoweringHVX.cpp | 324 MVT HalfTy = MVT::getVectorVT(VecTy.getVectorElementType(), NumElem/2); in typeSplit() local
325 return { HalfTy, HalfTy }; in typeSplit()
1306 MVT HalfTy = typeSplit(VecTy).first; in LowerHvxConcatVectors() local
1307 SDValue V0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfTy, in LowerHvxConcatVectors()
1309 SDValue V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfTy, in LowerHvxConcatVectors()
1783 MVT HalfTy = typeSplit(ResTy).first; in SplitHvxPairOp() local
1784 SDValue L = DAG.getNode(Op.getOpcode(), dl, HalfTy, OpsL); in SplitHvxPairOp()
1785 SDValue H = DAG.getNode(Op.getOpcode(), dl, HalfTy, OpsH); in SplitHvxPairOp()
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| D | HexagonISelDAGToDAGHVX.cpp | 992 MVT HalfTy = MVT::getVectorVT(OpTy.getVectorElementType(), in materialize() local
996 Op = DAG.getTargetExtractSubreg(Sub, dl, HalfTy, Op); in materialize()
1148 MVT HalfTy = getSingleVT(MVT::i8); in packp() local
1151 OpRef Out[2] = { OpRef::undef(HalfTy), OpRef::undef(HalfTy) }; in packp()
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| /external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | LegalizerHelper.h | 313 LLT HalfTy, LLT ShiftAmtTy);
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| /external/llvm/unittests/IR/ |
| D | InstructionsTest.cpp | 182 Type *HalfTy = Type::getHalfTy(C); in TEST() local
248 EXPECT_TRUE(CastInst::isBitCastable(Int16Ty, HalfTy)); in TEST()
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| /external/clang/include/clang/AST/ |
| D | BuiltinTypes.def | 125 FLOATING_TYPE(Half, HalfTy)
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| /external/llvm-project/clang/lib/AST/ |
| D | PrintfFormatString.cpp | 580 return Ctx.HalfTy; in getScalarArgType()
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