1 //===- AMDGPURegisterBankInfo -----------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file declares the targeting of the RegisterBankInfo class for AMDGPU. 10 /// \todo This should be generated by TableGen. 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H 14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H 15 16 #include "llvm/ADT/SmallSet.h" 17 #include "llvm/CodeGen/MachineBasicBlock.h" 18 #include "llvm/CodeGen/Register.h" 19 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" 20 21 #define GET_REGBANK_DECLARATIONS 22 #include "AMDGPUGenRegisterBank.inc" 23 #undef GET_REGBANK_DECLARATIONS 24 25 namespace llvm { 26 27 class LLT; 28 class GCNSubtarget; 29 class MachineIRBuilder; 30 class SIInstrInfo; 31 class SIRegisterInfo; 32 class TargetRegisterInfo; 33 34 /// This class provides the information for the target register banks. 35 class AMDGPUGenRegisterBankInfo : public RegisterBankInfo { 36 37 protected: 38 39 #define GET_TARGET_REGBANK_CLASS 40 #include "AMDGPUGenRegisterBank.inc" 41 }; 42 class AMDGPURegisterBankInfo final : public AMDGPUGenRegisterBankInfo { 43 public: 44 const GCNSubtarget &Subtarget; 45 const SIRegisterInfo *TRI; 46 const SIInstrInfo *TII; 47 48 bool buildVCopy(MachineIRBuilder &B, Register DstReg, Register SrcReg) const; 49 50 bool collectWaterfallOperands( 51 SmallSet<Register, 4> &SGPROperandRegs, 52 MachineInstr &MI, 53 MachineRegisterInfo &MRI, 54 ArrayRef<unsigned> OpIndices) const; 55 56 bool executeInWaterfallLoop( 57 MachineIRBuilder &B, 58 iterator_range<MachineBasicBlock::iterator> Range, 59 SmallSet<Register, 4> &SGPROperandRegs, 60 MachineRegisterInfo &MRI) const; 61 62 bool executeInWaterfallLoop(MachineIRBuilder &B, 63 MachineInstr &MI, 64 MachineRegisterInfo &MRI, 65 ArrayRef<unsigned> OpIndices) const; 66 bool executeInWaterfallLoop(MachineInstr &MI, 67 MachineRegisterInfo &MRI, 68 ArrayRef<unsigned> OpIndices) const; 69 70 void constrainOpWithReadfirstlane(MachineInstr &MI, MachineRegisterInfo &MRI, 71 unsigned OpIdx) const; 72 bool applyMappingDynStackAlloc(MachineInstr &MI, 73 const OperandsMapper &OpdMapper, 74 MachineRegisterInfo &MRI) const; 75 bool applyMappingLoad(MachineInstr &MI, 76 const OperandsMapper &OpdMapper, 77 MachineRegisterInfo &MRI) const; 78 bool 79 applyMappingImage(MachineInstr &MI, 80 const OperandsMapper &OpdMapper, 81 MachineRegisterInfo &MRI, int RSrcIdx) const; 82 bool applyMappingSBufferLoad(const OperandsMapper &OpdMapper) const; 83 84 bool applyMappingBFEIntrinsic(const OperandsMapper &OpdMapper, 85 bool Signed) const; 86 87 void lowerScalarMinMax(MachineIRBuilder &B, MachineInstr &MI) const; 88 89 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI, 90 Register Reg) const; 91 92 std::pair<Register, unsigned> 93 splitBufferOffsets(MachineIRBuilder &B, Register Offset) const; 94 95 MachineInstr *selectStoreIntrinsic(MachineIRBuilder &B, 96 MachineInstr &MI) const; 97 98 /// See RegisterBankInfo::applyMapping. 99 void applyMappingImpl(const OperandsMapper &OpdMapper) const override; 100 101 const ValueMapping *getValueMappingForPtr(const MachineRegisterInfo &MRI, 102 Register Ptr) const; 103 104 const RegisterBankInfo::InstructionMapping & 105 getInstrMappingForLoad(const MachineInstr &MI) const; 106 107 unsigned getRegBankID(Register Reg, const MachineRegisterInfo &MRI, 108 unsigned Default = AMDGPU::VGPRRegBankID) const; 109 110 // Return a value mapping for an operand that is required to be an SGPR. 111 const ValueMapping *getSGPROpMapping(Register Reg, 112 const MachineRegisterInfo &MRI, 113 const TargetRegisterInfo &TRI) const; 114 115 // Return a value mapping for an operand that is required to be a VGPR. 116 const ValueMapping *getVGPROpMapping(Register Reg, 117 const MachineRegisterInfo &MRI, 118 const TargetRegisterInfo &TRI) const; 119 120 // Return a value mapping for an operand that is required to be a AGPR. 121 const ValueMapping *getAGPROpMapping(Register Reg, 122 const MachineRegisterInfo &MRI, 123 const TargetRegisterInfo &TRI) const; 124 125 /// Split 64-bit value \p Reg into two 32-bit halves and populate them into \p 126 /// Regs. This appropriately sets the regbank of the new registers. 127 void split64BitValueForMapping(MachineIRBuilder &B, 128 SmallVector<Register, 2> &Regs, 129 LLT HalfTy, 130 Register Reg) const; 131 132 template <unsigned NumOps> 133 struct OpRegBankEntry { 134 int8_t RegBanks[NumOps]; 135 int16_t Cost; 136 }; 137 138 template <unsigned NumOps> 139 InstructionMappings 140 addMappingFromTable(const MachineInstr &MI, const MachineRegisterInfo &MRI, 141 const std::array<unsigned, NumOps> RegSrcOpIdx, 142 ArrayRef<OpRegBankEntry<NumOps>> Table) const; 143 144 RegisterBankInfo::InstructionMappings 145 getInstrAlternativeMappingsIntrinsic( 146 const MachineInstr &MI, const MachineRegisterInfo &MRI) const; 147 148 RegisterBankInfo::InstructionMappings 149 getInstrAlternativeMappingsIntrinsicWSideEffects( 150 const MachineInstr &MI, const MachineRegisterInfo &MRI) const; 151 152 unsigned getMappingType(const MachineRegisterInfo &MRI, 153 const MachineInstr &MI) const; 154 155 bool isSALUMapping(const MachineInstr &MI) const; 156 157 const InstructionMapping &getDefaultMappingSOP(const MachineInstr &MI) const; 158 const InstructionMapping &getDefaultMappingVOP(const MachineInstr &MI) const; 159 const InstructionMapping &getDefaultMappingAllVGPR( 160 const MachineInstr &MI) const; 161 162 const InstructionMapping &getImageMapping(const MachineRegisterInfo &MRI, 163 const MachineInstr &MI, 164 int RsrcIdx) const; 165 166 public: 167 AMDGPURegisterBankInfo(const GCNSubtarget &STI); 168 169 unsigned copyCost(const RegisterBank &A, const RegisterBank &B, 170 unsigned Size) const override; 171 172 unsigned getBreakDownCost(const ValueMapping &ValMapping, 173 const RegisterBank *CurBank = nullptr) const override; 174 175 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, 176 LLT) const override; 177 178 InstructionMappings 179 getInstrAlternativeMappings(const MachineInstr &MI) const override; 180 181 const InstructionMapping & 182 getInstrMapping(const MachineInstr &MI) const override; 183 184 private: 185 186 bool foldExtractEltToCmpSelect(MachineInstr &MI, 187 MachineRegisterInfo &MRI, 188 const OperandsMapper &OpdMapper) const; 189 bool foldInsertEltToCmpSelect(MachineInstr &MI, 190 MachineRegisterInfo &MRI, 191 const OperandsMapper &OpdMapper) const; 192 }; 193 } // End llvm namespace. 194 #endif 195