| /external/igt-gpu-tools/tests/i915/ |
| D | gem_set_tiling_vs_blt.c | 142 if (tiling == I915_TILING_NONE) { in do_test()
154 if (intel_gen(devid) >= 4 && tiling != I915_TILING_NONE) { in do_test()
244 tiling = I915_TILING_NONE;
247 igt_assert(tiling == I915_TILING_NONE);
253 tiling_after = I915_TILING_NONE;
256 igt_assert(tiling_after == I915_TILING_NONE);
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| D | gem_render_linear_blits.c | 112 src.tiling = I915_TILING_NONE; in run_test()
118 dst.tiling = I915_TILING_NONE; in run_test()
137 src.tiling = I915_TILING_NONE; in run_test()
143 dst.tiling = I915_TILING_NONE; in run_test()
164 src.tiling = I915_TILING_NONE; in run_test()
170 dst.tiling = I915_TILING_NONE; in run_test()
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| D | gem_stress.c | 288 if (src->tiling == I915_TILING_NONE) { in prw_copyfunc()
303 if (dst->tiling == I915_TILING_NONE) { in prw_copyfunc()
390 && options.forced_tiling != I915_TILING_NONE) { in next_copyfunc()
503 buf->tiling = I915_TILING_NONE; in init_buffer()
555 buffers[set][i].tiling = I915_TILING_NONE; in init_set()
560 if (buffers[set][i].tiling == I915_TILING_NONE) { in init_set()
693 options.forced_tiling = I915_TILING_NONE; in parse_options()
706 options.forced_tiling = I915_TILING_NONE; in parse_options()
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| D | i915_fb_tiling.c | 41 ret = __gem_set_tiling(drm_fd, fb.gem_handle, I915_TILING_NONE, fb.strides[0]);
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| D | gem_gtt_speed.c | 132 for (tiling = I915_TILING_NONE; tiling <= I915_TILING_Y; tiling++) {
133 if (tiling != I915_TILING_NONE) {
139 if (tiling == I915_TILING_NONE) {
450 if (tiling == I915_TILING_NONE) {
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| D | gem_fence_thrash.c | 240 igt_assert(run_test(0, bo_write_verify, I915_TILING_NONE, 80) == 0);
249 igt_assert(run_test(5, bo_write_verify, I915_TILING_NONE, 2) == 0);
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| D | gem_render_copy.c | 557 .tiling = I915_TILING_NONE, in test()
592 scratch_buf_init(data, &ref, WIDTH, HEIGHT, I915_TILING_NONE, false); in test()
721 test(&data, I915_TILING_NONE, 0);
730 test(&data, I915_TILING_NONE, I915_TILING_Y);
739 test(&data, I915_TILING_NONE, I915_TILING_Yf);
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| D | gem_mmap_gtt.c | 663 gem_set_tiling(fd, bo, I915_TILING_NONE, 0); in test_huge_bo()
992 test_huge_bo(fd, -1, I915_TILING_NONE);
999 test_huge_bo(fd, 0, I915_TILING_NONE);
1006 test_huge_bo(fd, 1, I915_TILING_NONE);
1028 { "", I915_TILING_NONE, I915_TILING_NONE},
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| D | gem_set_tiling_vs_pwrite.c | 84 gem_set_tiling(fd, handle, I915_TILING_NONE, 0);
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| D | gem_ppgtt.c | 77 buf->tiling = I915_TILING_NONE; in scratch_buf_init()
144 buf.tiling = I915_TILING_NONE; in fork_rcs_copy()
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| D | gem_set_tiling_vs_gtt.c | 118 gem_set_tiling(fd, handle, I915_TILING_NONE, 0);
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| /external/mesa3d/src/intel/isl/ |
| D | isl_drm.c | 38 return I915_TILING_NONE; in isl_tiling_to_i915_tiling()
52 return I915_TILING_NONE; in isl_tiling_to_i915_tiling()
62 case I915_TILING_NONE: in isl_tiling_from_i915_tiling()
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| /external/mesa3d/src/mesa/drivers/dri/i915/ |
| D | intel_blit.c | 101 if (dst_tiling != I915_TILING_NONE) { in emit_copy_blit()
105 if (src_tiling != I915_TILING_NONE) { in emit_copy_blit()
512 if (dst_tiling != I915_TILING_NONE) { in intelEmitImmediateColorExpandBlit()
542 if (dst_tiling != I915_TILING_NONE) in intelEmitImmediateColorExpandBlit()
592 pitch, src_bo, src_offset, I915_TILING_NONE, in intel_emit_linear_blit()
593 pitch, dst_bo, dst_offset, I915_TILING_NONE, in intel_emit_linear_blit()
608 pitch, src_bo, src_offset, I915_TILING_NONE, in intel_emit_linear_blit()
609 pitch, dst_bo, dst_offset, I915_TILING_NONE, in intel_emit_linear_blit()
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| D | intel_mipmap_tree.c | 137 return I915_TILING_NONE; in intel_miptree_choose_tiling()
144 return I915_TILING_NONE; in intel_miptree_choose_tiling()
149 return I915_TILING_NONE; in intel_miptree_choose_tiling()
243 if (tiling != I915_TILING_NONE) in intel_miptree_create_for_bo()
676 if (mt->region->tiling != I915_TILING_NONE) in intel_miptree_map_raw()
874 if (mt->region->tiling != I915_TILING_NONE && in intel_miptree_map()
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| D | intel_regions.c | 295 case I915_TILING_NONE: in intel_region_get_tile_masks()
325 case I915_TILING_NONE: in intel_region_get_aligned_offset()
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| /external/minigbm/ |
| D | i915.c | 125 struct format_metadata metadata_linear = { .tiling = I915_TILING_NONE, in i915_add_combinations()
206 case I915_TILING_NONE: in i915_align_dimensions()
253 if (i915->is_adlp && (*stride > 1) && (tiling != I915_TILING_NONE)) in i915_align_dimensions()
344 if (bo->meta.tiling != I915_TILING_NONE) in i915_bo_from_format()
423 bo->meta.tiling = I915_TILING_NONE; in i915_bo_compute_metadata()
595 if (bo->meta.tiling == I915_TILING_NONE) { in i915_bo_map()
655 if (bo->meta.tiling == I915_TILING_NONE) { in i915_bo_invalidate()
677 if (!i915->has_llc && bo->meta.tiling == I915_TILING_NONE) in i915_bo_flush()
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| /external/igt-gpu-tools/benchmarks/ |
| D | gem_mmap.c | 61 int tiling = I915_TILING_NONE; in main()
102 tiling = I915_TILING_NONE; in main()
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| /external/igt-gpu-tools/lib/ |
| D | igt_draw.c | 344 if (tiling != I915_TILING_NONE) in draw_rect_mmap_cpu()
350 case I915_TILING_NONE: in draw_rect_mmap_cpu()
395 if (tiling != I915_TILING_NONE) in draw_rect_mmap_wc()
402 case I915_TILING_NONE: in draw_rect_mmap_wc()
503 case I915_TILING_NONE: in draw_rect_pwrite()
605 src_buf.tiling = I915_TILING_NONE; in draw_rect_render()
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| D | intel_batchbuffer.c | 415 if (gen >= 4 && src_tiling != I915_TILING_NONE) { in intel_blt_copy()
420 if (gen >= 4 && dst_tiling != I915_TILING_NONE) { in intel_blt_copy()
537 if (tiling != I915_TILING_NONE) in fast_copy_pitch()
561 case I915_TILING_NONE: in fast_copy_dword0()
577 case I915_TILING_NONE: in fast_copy_dword0()
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| D | rendercopy_i915.c | 95 if (src->tiling != I915_TILING_NONE) in gen3_render_copyfunc()
142 if (dst->tiling != I915_TILING_NONE) in gen3_render_copyfunc()
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| D | rendercopy_i830.c | 153 if (dst->tiling != I915_TILING_NONE) in gen2_emit_target()
194 if (src->tiling != I915_TILING_NONE) in gen2_emit_texture()
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| /external/libdrm/intel/ |
| D | intel_bufmgr.c | 245 *tiling_mode = I915_TILING_NONE; in drm_intel_bo_set_tiling()
256 *tiling_mode = I915_TILING_NONE; in drm_intel_bo_get_tiling()
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| D | intel_bufmgr_gem.c | 320 if (*tiling_mode == I915_TILING_NONE) in drm_intel_gem_bo_tile_size()
337 *tiling_mode = I915_TILING_NONE; in drm_intel_gem_bo_tile_size()
366 if (*tiling_mode == I915_TILING_NONE) in drm_intel_gem_bo_tile_pitch()
384 *tiling_mode = I915_TILING_NONE; in drm_intel_gem_bo_tile_pitch()
587 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE) { in drm_intel_bo_gem_set_in_aperture_size()
821 bo_gem->tiling_mode = I915_TILING_NONE; in drm_intel_gem_bo_alloc_internal()
862 I915_TILING_NONE, 0, in drm_intel_gem_bo_alloc_for_render()
873 I915_TILING_NONE, 0, 0); in drm_intel_gem_bo_alloc()
904 if ((bufmgr_gem->gen == 2) && tiling != I915_TILING_NONE) in drm_intel_gem_bo_alloc_tiled()
921 if (tiling == I915_TILING_NONE) in drm_intel_gem_bo_alloc_tiled()
[all …]
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| /external/igt-gpu-tools/tests/ |
| D | kms_atomic.c | 297 w, h, format_primary, I915_TILING_NONE, in plane_primary_overlay_zpos()
302 format_overlay, I915_TILING_NONE, in plane_primary_overlay_zpos()
376 format, I915_TILING_NONE, &fb); in plane_overlay()
411 fb->drm_format, I915_TILING_NONE, in plane_primary()
460 format, I915_TILING_NONE, &fb); in test_only()
597 fb->drm_format, I915_TILING_NONE, &fb2); in plane_invalid_params()
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| D | brw_bufmgr.c | 211 if (tiling == I915_TILING_NONE) in bo_tile_size()
231 if (tiling == I915_TILING_NONE) in bo_tile_pitch()
648 bo->tiling_mode = I915_TILING_NONE; in bo_alloc_internal()
703 0, I915_TILING_NONE, 0); in brw_bo_alloc()
751 if (tiling == I915_TILING_NONE) in brw_bo_alloc_tiled_2d()
1260 if (bo->tiling_mode != I915_TILING_NONE && !(flags & MAP_RAW)) in brw_bo_map()
1555 assert(tiling_mode == I915_TILING_NONE || in brw_bo_gem_create_from_prime_tiled()
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