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Searched refs:IN0 (Results 1 – 10 of 10) sorted by relevance

/external/boringssl/src/crypto/fipsmodule/modes/asm/
Dghashp8-ppc.pl377 my $IN0=$IN;
441 lvx_u $IN0,0,$inp # load input
447 le?vperm $IN0,$IN0,$IN0,$lemask
452 vxor $Xh,$IN0,$Xl
475 lvx_u $IN0,0,$inp
484 le?vperm $IN0,$IN0,$IN0,$lemask
518 vxor $Xh,$Xh,$IN0
552 lvx_u $IN0,0,$inp
561 le?vperm $IN0,$IN0,$IN0,$lemask
565 vxor $Xh,$IN0,$Xl
[all …]
/external/webp/src/dsp/
Dcommon_sse41.h27 #define WEBP_SSE41_SHUFF(OUT, IN0, IN1) \ argument
28 OUT##0 = _mm_shuffle_epi8(*IN0, shuff0); \
29 OUT##1 = _mm_shuffle_epi8(*IN0, shuff1); \
30 OUT##2 = _mm_shuffle_epi8(*IN0, shuff2); \
/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
Dprelegalizercombiner-extending-loads-cornercases.mir115 # CHECK-WORKLIST: Try combining [[IN0:%[0-9]+]]:_(s8) = G_LOAD [[IN1:%[0-9]+]]:_(p0){{.*}} ::…
116 # CHECK-WORKLIST: Preferred use is: [[IN2:%[0-9]+]]:_(s32) = G_SEXT [[IN0]]:_(s8)
117 # CHECK-WORKLIST-DAG: Changing: [[IN0]]:_(s8) = G_LOAD [[IN1]]:_(p0){{.*}} :: (load 1 from %ir.ad…
118 # CHECK-WORKLIST-DAG: Changing: [[IN3:%[0-9]+]]:_(s8) = G_ADD [[IN0]]:_, [[IN4:%[0-9]+]]:_
120 # CHECK-WORKLIST-DAG: Changing: [[IN5:%[0-9]+]]:_(s8) = G_SUB [[IN0]]:_, [[IN6:%[0-9]+]]:_
122 # CHECK-WORKLIST-DAG: Erasing: [[IN2]]:_(s32) = G_SEXT [[IN0]]:_(s8)
214 # CHECK-WORKLIST: Try combining [[IN0:%[0-9]+]]:_(s8) = G_LOAD [[IN1:%[0-9]+]]:_(p0){{.*}} ::…
215 # CHECK-WORKLIST: Preferred use is: [[IN2:%[0-9]+]]:_(s32) = G_SEXT [[IN0]]:_(s8)
216 # CHECK-WORKLIST-DAG: Changing: [[IN0]]:_(s8) = G_LOAD [[IN1]]:_(p0){{.*}} :: (load 1 from %ir.ad…
218 # CHECK-WORKLIST-DAG: Changing: [[IN3:%[0-9]+]]:_(s8) = G_ADD [[IN0]]:_, [[IN4:%[0-9]+]]:_
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dvtx-schedule.ll9 ; CHECK: VTX_READ_32 [[IN0:T[0-9]+\.X]], [[IN0]], 0
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dvtx-schedule.ll9 ; CHECK: VTX_READ_32 [[IN0:T[0-9]+\.X]], [[IN0]], 0
Dfabs.f16.ll56 ; GCN: s_load_dword [[IN0:s[0-9]+]]
57 ; GCN-DAG: s_lshr_b32 [[IN1:s[0-9]+]], [[IN0]], 16
59 ; CI-DAG: v_cvt_f32_f16_e64 [[CVT0:v[0-9]+]], |[[IN0]]|
67 ; GFX89: v_mul_f16_e64 [[RESULT:v[0-9]+]], |[[IN0]]|, [[V_IN1]]
Dindirect-addressing-si.ll10 ; GCN-DAG: s_load_dword [[IN0:s[0-9]+]]
15 ; GCN-DAG: s_add_i32 [[IN:s[0-9]+]], [[IN0]], 1
168 ; GCN-DAG: s_load_dword [[IN0:s[0-9]+]]
169 ; MOVREL-DAG: s_add_i32 [[IN:s[0-9]+]], [[IN0]], 1
Dlower-kernargs.ll1859 ; HSA-NEXT: [[IN0:%.*]] = load i32, i32 addrspace(4)* [[TMP1]], align 4
1861 ; HSA-NEXT: store volatile i32 [[IN0]], i32 addrspace(1)* [[OUT_LOAD]], align 4
1878 ; MESA-NEXT: [[IN0:%.*]] = load i32, i32 addrspace(4)* [[TMP1]], align 4
1880 ; MESA-NEXT: store volatile i32 [[IN0]], i32 addrspace(1)* [[OUT_LOAD]], align 4
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dpr19420.ll26 ; CHECK-NEXT: [[TMP1:%.*]] = mul <16 x i8> [[IN0:%.*]], <i8 33, i8 33, i8 33, i8 33, i8 33, i8 3…
Dvec_shuffle.ll702 ; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[IN0:%.*]], <4 x i32> undef, <2 x i32> …
715 ; CHECK-NEXT: [[TMP1:%.*]] = mul <8 x i16> [[IN0:%.*]], [[IN1:%.*]]
727 ; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <16 x i8> [[IN0:%.*]], <16 x i8> undef, <8 x i32> …
738 ; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i32> [[IN0:%.*]], i32 0