1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -S -instcombine < %s | FileCheck %s 3 4define <4 x i32> @test_FoldShiftByConstant_CreateSHL(<4 x i32> %in) { 5; CHECK-LABEL: @test_FoldShiftByConstant_CreateSHL( 6; CHECK-NEXT: [[VSHL_N:%.*]] = mul <4 x i32> [[IN:%.*]], <i32 0, i32 -32, i32 0, i32 -32> 7; CHECK-NEXT: ret <4 x i32> [[VSHL_N]] 8; 9 %mul.i = mul <4 x i32> %in, <i32 0, i32 -1, i32 0, i32 -1> 10 %vshl_n = shl <4 x i32> %mul.i, <i32 5, i32 5, i32 5, i32 5> 11 ret <4 x i32> %vshl_n 12} 13 14define <8 x i16> @test_FoldShiftByConstant_CreateSHL2(<8 x i16> %in) { 15; CHECK-LABEL: @test_FoldShiftByConstant_CreateSHL2( 16; CHECK-NEXT: [[VSHL_N:%.*]] = mul <8 x i16> [[IN:%.*]], <i16 0, i16 -32, i16 0, i16 -32, i16 0, i16 -32, i16 0, i16 -32> 17; CHECK-NEXT: ret <8 x i16> [[VSHL_N]] 18; 19 %mul.i = mul <8 x i16> %in, <i16 0, i16 -1, i16 0, i16 -1, i16 0, i16 -1, i16 0, i16 -1> 20 %vshl_n = shl <8 x i16> %mul.i, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5> 21 ret <8 x i16> %vshl_n 22} 23 24define <16 x i8> @test_FoldShiftByConstant_CreateAnd(<16 x i8> %in0) { 25; CHECK-LABEL: @test_FoldShiftByConstant_CreateAnd( 26; CHECK-NEXT: [[TMP1:%.*]] = mul <16 x i8> [[IN0:%.*]], <i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33> 27; CHECK-NEXT: [[VSHL_N:%.*]] = and <16 x i8> [[TMP1]], <i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32> 28; CHECK-NEXT: ret <16 x i8> [[VSHL_N]] 29; 30 %vsra_n = ashr <16 x i8> %in0, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5> 31 %tmp = add <16 x i8> %in0, %vsra_n 32 %vshl_n = shl <16 x i8> %tmp, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5> 33 ret <16 x i8> %vshl_n 34} 35 36define i32 @lshr_add_shl(i32 %x, i32 %y) { 37; CHECK-LABEL: @lshr_add_shl( 38; CHECK-NEXT: [[B1:%.*]] = shl i32 [[Y:%.*]], 4 39; CHECK-NEXT: [[A2:%.*]] = add i32 [[B1]], [[X:%.*]] 40; CHECK-NEXT: [[C:%.*]] = and i32 [[A2]], -16 41; CHECK-NEXT: ret i32 [[C]] 42; 43 %a = lshr i32 %x, 4 44 %b = add i32 %a, %y 45 %c = shl i32 %b, 4 46 ret i32 %c 47} 48 49define <2 x i32> @lshr_add_shl_v2i32(<2 x i32> %x, <2 x i32> %y) { 50; CHECK-LABEL: @lshr_add_shl_v2i32( 51; CHECK-NEXT: [[B1:%.*]] = shl <2 x i32> [[Y:%.*]], <i32 5, i32 5> 52; CHECK-NEXT: [[A2:%.*]] = add <2 x i32> [[B1]], [[X:%.*]] 53; CHECK-NEXT: [[C:%.*]] = and <2 x i32> [[A2]], <i32 -32, i32 -32> 54; CHECK-NEXT: ret <2 x i32> [[C]] 55; 56 %a = lshr <2 x i32> %x, <i32 5, i32 5> 57 %b = add <2 x i32> %a, %y 58 %c = shl <2 x i32> %b, <i32 5, i32 5> 59 ret <2 x i32> %c 60} 61 62define <2 x i32> @lshr_add_shl_v2i32_undef(<2 x i32> %x, <2 x i32> %y) { 63; CHECK-LABEL: @lshr_add_shl_v2i32_undef( 64; CHECK-NEXT: [[A:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 5, i32 undef> 65; CHECK-NEXT: [[B:%.*]] = add <2 x i32> [[A]], [[Y:%.*]] 66; CHECK-NEXT: [[C:%.*]] = shl <2 x i32> [[B]], <i32 undef, i32 5> 67; CHECK-NEXT: ret <2 x i32> [[C]] 68; 69 %a = lshr <2 x i32> %x, <i32 5, i32 undef> 70 %b = add <2 x i32> %a, %y 71 %c = shl <2 x i32> %b, <i32 undef, i32 5> 72 ret <2 x i32> %c 73} 74 75define <2 x i32> @lshr_add_shl_v2i32_nonuniform(<2 x i32> %x, <2 x i32> %y) { 76; CHECK-LABEL: @lshr_add_shl_v2i32_nonuniform( 77; CHECK-NEXT: [[A:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 5, i32 6> 78; CHECK-NEXT: [[B:%.*]] = add <2 x i32> [[A]], [[Y:%.*]] 79; CHECK-NEXT: [[C:%.*]] = shl <2 x i32> [[B]], <i32 5, i32 6> 80; CHECK-NEXT: ret <2 x i32> [[C]] 81; 82 %a = lshr <2 x i32> %x, <i32 5, i32 6> 83 %b = add <2 x i32> %a, %y 84 %c = shl <2 x i32> %b, <i32 5, i32 6> 85 ret <2 x i32> %c 86} 87 88define i32 @lshr_add_and_shl(i32 %x, i32 %y) { 89; CHECK-LABEL: @lshr_add_and_shl( 90; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[Y:%.*]], 5 91; CHECK-NEXT: [[X_MASK:%.*]] = and i32 [[X:%.*]], 4064 92; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[X_MASK]], [[TMP1]] 93; CHECK-NEXT: ret i32 [[TMP2]] 94; 95 %1 = lshr i32 %x, 5 96 %2 = and i32 %1, 127 97 %3 = add i32 %y, %2 98 %4 = shl i32 %3, 5 99 ret i32 %4 100} 101 102define <2 x i32> @lshr_add_and_shl_v2i32(<2 x i32> %x, <2 x i32> %y) { 103; CHECK-LABEL: @lshr_add_and_shl_v2i32( 104; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> [[Y:%.*]], <i32 5, i32 5> 105; CHECK-NEXT: [[X_MASK:%.*]] = and <2 x i32> [[X:%.*]], <i32 4064, i32 4064> 106; CHECK-NEXT: [[TMP2:%.*]] = add <2 x i32> [[X_MASK]], [[TMP1]] 107; CHECK-NEXT: ret <2 x i32> [[TMP2]] 108; 109 %1 = lshr <2 x i32> %x, <i32 5, i32 5> 110 %2 = and <2 x i32> %1, <i32 127, i32 127> 111 %3 = add <2 x i32> %y, %2 112 %4 = shl <2 x i32> %3, <i32 5, i32 5> 113 ret <2 x i32> %4 114} 115 116define <2 x i32> @lshr_add_and_shl_v2i32_undef(<2 x i32> %x, <2 x i32> %y) { 117; CHECK-LABEL: @lshr_add_and_shl_v2i32_undef( 118; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 undef, i32 5> 119; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], <i32 127, i32 127> 120; CHECK-NEXT: [[TMP3:%.*]] = add <2 x i32> [[TMP2]], [[Y:%.*]] 121; CHECK-NEXT: [[TMP4:%.*]] = shl <2 x i32> [[TMP3]], <i32 5, i32 undef> 122; CHECK-NEXT: ret <2 x i32> [[TMP4]] 123; 124 %1 = lshr <2 x i32> %x, <i32 undef, i32 5> 125 %2 = and <2 x i32> %1, <i32 127, i32 127> 126 %3 = add <2 x i32> %y, %2 127 %4 = shl <2 x i32> %3, <i32 5, i32 undef> 128 ret <2 x i32> %4 129} 130 131define <2 x i32> @lshr_add_and_shl_v2i32_nonuniform(<2 x i32> %x, <2 x i32> %y) { 132; CHECK-LABEL: @lshr_add_and_shl_v2i32_nonuniform( 133; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 5, i32 6> 134; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], <i32 127, i32 255> 135; CHECK-NEXT: [[TMP3:%.*]] = add <2 x i32> [[TMP2]], [[Y:%.*]] 136; CHECK-NEXT: [[TMP4:%.*]] = shl <2 x i32> [[TMP3]], <i32 5, i32 6> 137; CHECK-NEXT: ret <2 x i32> [[TMP4]] 138; 139 %1 = lshr <2 x i32> %x, <i32 5, i32 6> 140 %2 = and <2 x i32> %1, <i32 127, i32 255> 141 %3 = add <2 x i32> %y, %2 142 %4 = shl <2 x i32> %3, <i32 5, i32 6> 143 ret <2 x i32> %4 144} 145 146define i32 @shl_add_and_lshr(i32 %x, i32 %y) { 147; CHECK-LABEL: @shl_add_and_lshr( 148; CHECK-NEXT: [[C1:%.*]] = shl i32 [[Y:%.*]], 4 149; CHECK-NEXT: [[X_MASK:%.*]] = and i32 [[X:%.*]], 128 150; CHECK-NEXT: [[D:%.*]] = add i32 [[X_MASK]], [[C1]] 151; CHECK-NEXT: ret i32 [[D]] 152; 153 %a = lshr i32 %x, 4 154 %b = and i32 %a, 8 155 %c = add i32 %b, %y 156 %d = shl i32 %c, 4 157 ret i32 %d 158} 159 160define <2 x i32> @shl_add_and_lshr_v2i32(<2 x i32> %x, <2 x i32> %y) { 161; CHECK-LABEL: @shl_add_and_lshr_v2i32( 162; CHECK-NEXT: [[C1:%.*]] = shl <2 x i32> [[Y:%.*]], <i32 4, i32 4> 163; CHECK-NEXT: [[X_MASK:%.*]] = and <2 x i32> [[X:%.*]], <i32 128, i32 128> 164; CHECK-NEXT: [[D:%.*]] = add <2 x i32> [[X_MASK]], [[C1]] 165; CHECK-NEXT: ret <2 x i32> [[D]] 166; 167 %a = lshr <2 x i32> %x, <i32 4, i32 4> 168 %b = and <2 x i32> %a, <i32 8, i32 8> 169 %c = add <2 x i32> %b, %y 170 %d = shl <2 x i32> %c, <i32 4, i32 4> 171 ret <2 x i32> %d 172} 173 174define <2 x i32> @shl_add_and_lshr_v2i32_undef(<2 x i32> %x, <2 x i32> %y) { 175; CHECK-LABEL: @shl_add_and_lshr_v2i32_undef( 176; CHECK-NEXT: [[A:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 4, i32 undef> 177; CHECK-NEXT: [[B:%.*]] = and <2 x i32> [[A]], <i32 8, i32 undef> 178; CHECK-NEXT: [[C:%.*]] = add <2 x i32> [[B]], [[Y:%.*]] 179; CHECK-NEXT: [[D:%.*]] = shl <2 x i32> [[C]], <i32 4, i32 undef> 180; CHECK-NEXT: ret <2 x i32> [[D]] 181; 182 %a = lshr <2 x i32> %x, <i32 4, i32 undef> 183 %b = and <2 x i32> %a, <i32 8, i32 undef> 184 %c = add <2 x i32> %b, %y 185 %d = shl <2 x i32> %c, <i32 4, i32 undef> 186 ret <2 x i32> %d 187} 188 189define <2 x i32> @shl_add_and_lshr_v2i32_nonuniform(<2 x i32> %x, <2 x i32> %y) { 190; CHECK-LABEL: @shl_add_and_lshr_v2i32_nonuniform( 191; CHECK-NEXT: [[A:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 4, i32 5> 192; CHECK-NEXT: [[B:%.*]] = and <2 x i32> [[A]], <i32 8, i32 9> 193; CHECK-NEXT: [[C:%.*]] = add <2 x i32> [[B]], [[Y:%.*]] 194; CHECK-NEXT: [[D:%.*]] = shl <2 x i32> [[C]], <i32 4, i32 5> 195; CHECK-NEXT: ret <2 x i32> [[D]] 196; 197 %a = lshr <2 x i32> %x, <i32 4, i32 5> 198 %b = and <2 x i32> %a, <i32 8, i32 9> 199 %c = add <2 x i32> %b, %y 200 %d = shl <2 x i32> %c, <i32 4, i32 5> 201 ret <2 x i32> %d 202} 203