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Searched refs:IR3_REG_SSA (Results 1 – 10 of 10) sorted by relevance

/external/mesa3d/src/freedreno/ir3/
Dir3_context.c460 instr->regs[0]->flags &= ~IR3_REG_SSA; in create_addr0()
472 instr->regs[0]->flags &= ~IR3_REG_SSA; in create_addr1()
535 cond->regs[0]->flags &= ~IR3_REG_SSA; in ir3_get_predicate()
666 ir3_reg_create(mov, 0, IR3_REG_SSA | flags)->instr = src; in ir3_create_array_store()
Dir3_cp.c129 *dstflags &= ~IR3_REG_SSA; in combine_flags()
130 *dstflags |= srcflags & IR3_REG_SSA; in combine_flags()
Dir3.h108 IR3_REG_SSA = 0x4000, /* 'instr' is ptr to assigning instr */ enumerator
954 if (reg->flags & (IR3_REG_SSA | IR3_REG_ARRAY)) { in ssa()
1359 reg = ir3_reg_create(instr, 0, IR3_REG_SSA | flags); in __ssa_src()
1368 reg->flags |= IR3_REG_SSA; in __ssa_dst()
Dir3_print.c196 } else if (reg->flags & IR3_REG_SSA) { in print_reg_name()
Dir3_ra.c1143 reg->flags &= ~IR3_REG_SSA; in reg_assign()
1176 reg->flags &= ~IR3_REG_SSA; in reg_assign()
Dir3_sched.c906 if (!(instr->regs[0]->flags & IR3_REG_SSA)) in is_output_only()
Dir3.c1345 if (instr->regs[n+1]->flags & IR3_REG_SSA) { in ir3_valid_flags()
Dir3_compiler_nir.c1898 cond->regs[0]->flags &= ~IR3_REG_SSA; in emit_intrinsic()
2799 cond->regs[0]->flags &= ~IR3_REG_SSA; in emit_stream_out()
/external/mesa3d/src/freedreno/ir3/tests/
Ddelay.c149 reg->flags |= IR3_REG_SSA; in regs_to_ssa()
/external/mesa3d/docs/drivers/freedreno/
Dir3-notes.rst44 …s. And additionally, for normal (non-const, etc) src registers, the ``IR3_REG_SSA`` flag is set a…
113 If ``IR3_REG_SSA`` is set on a src register, the actual register