| /external/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 70 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset = 0) const;
119 static bool isDispOrCDisp8(uint64_t TSFlags, int Value, int &ImmOffset) { in isDispOrCDisp8() argument
136 ImmOffset = CDisp8 - Value; in isDispOrCDisp8()
291 int ImmOffset) const { in emitImmediate()
298 emitConstant(DispOp.getImm() + ImmOffset, Size, OS); in emitImmediate()
311 assert(ImmOffset == 0); in emitImmediate()
321 ImmOffset = static_cast<int>(OS.tell() - StartByte); in emitImmediate()
343 ImmOffset -= 4; in emitImmediate()
351 ImmOffset -= 2; in emitImmediate()
353 ImmOffset -= 1; in emitImmediate()
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 106 int ImmOffset = 0) const;
280 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const { in EmitImmediate()
288 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS); in EmitImmediate()
302 assert(ImmOffset == 0); in EmitImmediate()
312 ImmOffset = CurByte; in EmitImmediate()
333 ImmOffset -= 4; in EmitImmediate()
335 ImmOffset -= 2; in EmitImmediate()
337 ImmOffset -= 1; in EmitImmediate()
339 if (ImmOffset) in EmitImmediate()
340 Expr = MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(ImmOffset, Ctx), in EmitImmediate()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 91 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset = 0) const;
295 int ImmOffset) const { in emitImmediate()
302 emitConstant(DispOp.getImm() + ImmOffset, Size, CurByte, OS); in emitImmediate()
315 assert(ImmOffset == 0); in emitImmediate()
325 ImmOffset = CurByte; in emitImmediate()
347 ImmOffset -= 4; in emitImmediate()
355 ImmOffset -= 2; in emitImmediate()
357 ImmOffset -= 1; in emitImmediate()
359 if (ImmOffset) in emitImmediate()
360 Expr = MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(ImmOffset, Ctx), in emitImmediate()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 103 SDValue &SOffset, SDValue &ImmOffset) const;
113 SDValue &ImmOffset) const;
115 SDValue &ImmOffset) const;
117 SDValue &ImmOffset, SDValue &VOffset) const;
908 SDValue &ImmOffset) const { in SelectMUBUFScratch()
926 ImmOffset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16); in SelectMUBUFScratch()
933 ImmOffset = CurDAG->getTargetConstant(0, DL, MVT::i16); in SelectMUBUFScratch()
982 SDValue &ImmOffset) const { in SelectMUBUFConstant()
1012 ImmOffset = CurDAG->getTargetConstant(Imm, DL, MVT::i16); in SelectMUBUFConstant()
1026 SDValue &ImmOffset) const { in SelectMUBUFIntrinsicOffset()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPURegisterBankInfo.cpp | 1335 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
1336 if (AMDGPU::splitMUBUFOffset(*Imm, SOffset, ImmOffset, &RBI.Subtarget, in setBufferOffsets()
1340 InstOffsetVal = ImmOffset; in setBufferOffsets()
1344 return SOffset + ImmOffset; in setBufferOffsets()
1354 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
1355 if (Offset > 0 && AMDGPU::splitMUBUFOffset(Offset, SOffset, ImmOffset, in setBufferOffsets()
1361 InstOffsetVal = ImmOffset; in setBufferOffsets()
1370 InstOffsetVal = ImmOffset; in setBufferOffsets()
1446 int64_t ImmOffset = 0; in applyMappingSBufferLoad() local
1449 VOffset, SOffset, ImmOffset, Alignment); in applyMappingSBufferLoad()
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| D | AMDGPUISelDAGToDAG.cpp | 229 SDValue &SOffset, SDValue &ImmOffset) const;
1560 SDValue &ImmOffset) const { in SelectMUBUFScratchOffen()
1586 ImmOffset = CurDAG->getTargetConstant(Imm & 4095, DL, MVT::i16); in SelectMUBUFScratchOffen()
1617 ImmOffset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16); in SelectMUBUFScratchOffen()
1624 ImmOffset = CurDAG->getTargetConstant(0, DL, MVT::i16); in SelectMUBUFScratchOffen()
1820 int64_t ImmOffset = 0; in SelectGlobalSAddr() local
1832 ImmOffset = COffsetVal; in SelectGlobalSAddr()
1866 Offset = CurDAG->getTargetConstant(ImmOffset, SDLoc(), MVT::i16); in SelectGlobalSAddr()
1892 Offset = CurDAG->getTargetConstant(ImmOffset, SDLoc(), MVT::i16); in SelectGlobalSAddr()
2516 int ImmOffset = 0; in SelectDS_GWS() local
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| D | AMDGPULegalizerInfo.cpp | 3496 unsigned ImmOffset = TotalConstOffset; in splitBufferOffsets() local
3505 unsigned Overflow = ImmOffset & ~MaxImm; in splitBufferOffsets()
3506 ImmOffset -= Overflow; in splitBufferOffsets()
3508 Overflow += ImmOffset; in splitBufferOffsets()
3509 ImmOffset = 0; in splitBufferOffsets()
3524 return std::make_tuple(BaseReg, ImmOffset, TotalConstOffset); in splitBufferOffsets()
3624 unsigned ImmOffset; in legalizeBufferStore() local
3650 std::tie(VOffset, ImmOffset, TotalOffset) = splitBufferOffsets(B, VOffset); in legalizeBufferStore()
3684 .addImm(ImmOffset); // offset(imm) in legalizeBufferStore()
3732 unsigned ImmOffset; in legalizeBufferLoad() local
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| D | AMDGPUInstructionSelector.cpp | 1326 unsigned ImmOffset; in selectDSGWSIntrinsic() local
1348 ImmOffset = OffsetDef->getOperand(1).getCImm()->getZExtValue(); in selectDSGWSIntrinsic()
1352 std::tie(BaseOffset, ImmOffset) = in selectDSGWSIntrinsic()
1390 MIB.addImm(ImmOffset) in selectDSGWSIntrinsic()
3490 int64_t ImmOffset = 0; in selectGlobalSAddr() local
3499 ImmOffset = ConstOffset; in selectGlobalSAddr()
3563 [=](MachineInstrBuilder &MIB) { MIB.addImm(ImmOffset); } // offset in selectGlobalSAddr()
3588 MIB.addImm(ImmOffset); in selectGlobalSAddr()
3977 MachineIRBuilder &B, Register &SOffset, int64_t &ImmOffset) const { in splitIllegalMUBUFOffset()
3978 if (SIInstrInfo::isLegalMUBUFImmOffset(ImmOffset)) in splitIllegalMUBUFOffset()
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| D | AMDGPUInstructionSelector.h | 243 Register &SOffset, int64_t &ImmOffset) const;
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| D | SIISelLowering.cpp | 7811 unsigned ImmOffset = C1->getZExtValue(); in splitBufferOffsets() local
7819 unsigned Overflow = ImmOffset & ~MaxImm; in splitBufferOffsets()
7820 ImmOffset -= Overflow; in splitBufferOffsets()
7822 Overflow += ImmOffset; in splitBufferOffsets()
7823 ImmOffset = 0; in splitBufferOffsets()
7825 C1 = cast<ConstantSDNode>(DAG.getTargetConstant(ImmOffset, DL, MVT::i32)); in splitBufferOffsets()
7852 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
7853 if (AMDGPU::splitMUBUFOffset(Imm, SOffset, ImmOffset, Subtarget, in setBufferOffsets()
7857 Offsets[2] = DAG.getTargetConstant(ImmOffset, DL, MVT::i32); in setBufferOffsets()
7858 return SOffset + ImmOffset; in setBufferOffsets()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 923 unsigned ImmOffset = TotalConstOffset; in splitBufferOffsets() local
932 unsigned Overflow = ImmOffset & ~MaxImm; in splitBufferOffsets()
933 ImmOffset -= Overflow; in splitBufferOffsets()
935 Overflow += ImmOffset; in splitBufferOffsets()
936 ImmOffset = 0; in splitBufferOffsets()
968 return std::make_tuple(BaseReg, ImmOffset, TotalConstOffset); in splitBufferOffsets()
990 unsigned ImmOffset; in selectStoreIntrinsic() local
993 std::tie(VOffset, ImmOffset, TotalOffset) = splitBufferOffsets(B, VOffset); in selectStoreIntrinsic()
1012 .addImm(ImmOffset) in selectStoreIntrinsic()
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| D | AMDGPURegisterBankInfo.cpp | 1301 unsigned ImmOffset; in splitBufferOffsets() local
1304 std::tie(BaseReg, ImmOffset) = getBaseWithConstantOffset(*B.getMRI(), in splitBufferOffsets()
1308 if (ImmOffset != 0) { in splitBufferOffsets()
1316 unsigned Overflow = ImmOffset & ~MaxImm; in splitBufferOffsets()
1317 ImmOffset -= Overflow; in splitBufferOffsets()
1319 Overflow += ImmOffset; in splitBufferOffsets()
1320 ImmOffset = 0; in splitBufferOffsets()
1323 C1 = ImmOffset; in splitBufferOffsets()
1384 unsigned ImmOffset; in selectStoreIntrinsic() local
1385 std::tie(VOffset, ImmOffset) = splitBufferOffsets(B, VOffset); in selectStoreIntrinsic()
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| D | AMDGPUISelDAGToDAG.cpp | 221 SDValue &SOffset, SDValue &ImmOffset) const;
1500 SDValue &ImmOffset) const { in SelectMUBUFScratchOffen()
1523 ImmOffset = CurDAG->getTargetConstant(Imm & 4095, DL, MVT::i16); in SelectMUBUFScratchOffen()
1553 ImmOffset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16); in SelectMUBUFScratchOffen()
1560 ImmOffset = CurDAG->getTargetConstant(0, DL, MVT::i16); in SelectMUBUFScratchOffen()
2286 int ImmOffset = 0; in SelectDS_GWS() local
2302 ImmOffset = ConstOffset->getZExtValue(); in SelectDS_GWS()
2305 ImmOffset = BaseOffset.getConstantOperandVal(1); in SelectDS_GWS()
2324 SDValue OffsetField = CurDAG->getTargetConstant(ImmOffset, SL, MVT::i32); in SelectDS_GWS()
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| D | SIISelLowering.cpp | 7150 unsigned ImmOffset = C1->getZExtValue(); in splitBufferOffsets() local
7158 unsigned Overflow = ImmOffset & ~MaxImm; in splitBufferOffsets()
7159 ImmOffset -= Overflow; in splitBufferOffsets()
7161 Overflow += ImmOffset; in splitBufferOffsets()
7162 ImmOffset = 0; in splitBufferOffsets()
7164 C1 = cast<ConstantSDNode>(DAG.getTargetConstant(ImmOffset, DL, MVT::i32)); in splitBufferOffsets()
7191 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
7192 if (AMDGPU::splitMUBUFOffset(Imm, SOffset, ImmOffset, Subtarget, Align)) { in setBufferOffsets()
7195 Offsets[2] = DAG.getTargetConstant(ImmOffset, DL, MVT::i32); in setBufferOffsets()
7196 return SOffset + ImmOffset; in setBufferOffsets()
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ExpandPseudoInsts.cpp | 615 int ImmOffset = MI.getOperand(2).getImm() + Offset; in expandSVESpillFill() local
617 assert(ImmOffset >= -256 && ImmOffset < 256 && in expandSVESpillFill()
624 .addImm(ImmOffset); in expandSVESpillFill()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceInstMIPS32.h | 130 Operand *ImmOffset, AddrMode Mode = Offset) {
132 OperandMIPS32Mem(Func, Ty, Base, ImmOffset, Mode);
136 Operand *getOffset() const { return ImmOffset; } in getOffset()
171 OperandMIPS32Mem(Cfg *Func, Type Ty, Variable *Base, Operand *ImmOffset,
175 Operand *const ImmOffset; variable
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| D | IceInstARM32.h | 106 ConstantInteger32 *ImmOffset,
109 OperandARM32Mem(Func, Ty, Base, ImmOffset, Mode);
121 ConstantInteger32 *getOffset() const { return ImmOffset; } in getOffset()
153 ConstantInteger32 *ImmOffset, AddrMode Mode);
158 ConstantInteger32 *ImmOffset; variable
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| D | IceInstMIPS32.cpp | 47 Operand *ImmOffset, AddrMode Mode) in OperandMIPS32Mem() argument
48 : OperandMIPS32(kMem, Ty), Base(Base), ImmOffset(ImmOffset), Mode(Mode) { in OperandMIPS32Mem()
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| D | IceInstARM32.cpp | 321 ConstantInteger32 *ImmOffset, AddrMode Mode) in OperandARM32Mem() argument
322 : OperandARM32(kMem, Ty), Base(Base), ImmOffset(ImmOffset), Index(nullptr), in OperandARM32Mem()
333 : OperandARM32(kMem, Ty), Base(Base), ImmOffset(0), Index(Index), in OperandARM32Mem()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Utils/ |
| D | AMDGPUBaseInfo.h | 660 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
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| D | AMDGPUBaseInfo.cpp | 1269 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, in splitMUBUFOffset() argument
1303 ImmOffset = Imm; in splitMUBUFOffset()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
| D | AMDGPUBaseInfo.h | 741 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
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| D | AMDGPUBaseInfo.cpp | 1527 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, in splitMUBUFOffset() argument
1561 ImmOffset = Imm; in splitMUBUFOffset()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 3698 SDValue Base, RegOffset, ImmOffset; in Select() local
3701 SelectAddrMode3(Addr, Base, RegOffset, ImmOffset); in Select()
3710 SDValue Ops[] = {Base, RegOffset, ImmOffset, Chain}; in Select()
3727 SDValue Base, RegOffset, ImmOffset; in Select() local
3730 SelectAddrMode3(Addr, Base, RegOffset, ImmOffset); in Select()
3741 SDValue Ops[] = {SDValue(RegPair, 0), Base, RegOffset, ImmOffset, Chain}; in Select()
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