Home
last modified time | relevance | path

Searched refs:InsnID (Results 1 – 25 of 25) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DInstructionSelectorImpl.h87 int64_t InsnID = MatchTable[CurrentIdx++]; in executeMatchTable() local
94 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx); in executeMatchTable()
120 << "] = GIM_RecordInsn(" << InsnID << ", " << OpIdx in executeMatchTable()
140 int64_t InsnID = MatchTable[CurrentIdx++]; in executeMatchTable() local
143 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); in executeMatchTable()
144 unsigned Opcode = State.MIs[InsnID]->getOpcode(); in executeMatchTable()
147 dbgs() << CurrentIdx << ": GIM_CheckOpcode(MIs[" << InsnID in executeMatchTable()
158 int64_t InsnID = MatchTable[CurrentIdx++]; in executeMatchTable() local
163 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); in executeMatchTable()
164 const int64_t Opcode = State.MIs[InsnID]->getOpcode(); in executeMatchTable()
[all …]
/external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
DInstructionSelectorImpl.h105 int64_t InsnID = MatchTable[CurrentIdx++]; in executeMatchTable() local
112 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx); in executeMatchTable()
138 << "] = GIM_RecordInsn(" << InsnID << ", " << OpIdx in executeMatchTable()
159 int64_t InsnID = MatchTable[CurrentIdx++]; in executeMatchTable() local
165 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); in executeMatchTable()
166 unsigned Opcode = State.MIs[InsnID]->getOpcode(); in executeMatchTable()
169 dbgs() << CurrentIdx << ": GIM_CheckOpcode(MIs[" << InsnID in executeMatchTable()
183 int64_t InsnID = MatchTable[CurrentIdx++]; in executeMatchTable() local
188 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); in executeMatchTable()
189 const int64_t Opcode = State.MIs[InsnID]->getOpcode(); in executeMatchTable()
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenGlobalISel.inc918 GIM_CheckIsSafeToFold, /*InsnID*/1,
920 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAB,
924 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
925 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
926 GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
927 GIR_EraseFromParent, /*InsnID*/0,
928 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
942 GIM_CheckIsSafeToFold, /*InsnID*/1,
944 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAH,
948 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenGlobalISel.inc1237 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWri,
1240 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
1241 GIR_EraseFromParent, /*InsnID*/0,
1242 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1251 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWri,
1254 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm
1255 GIR_EraseFromParent, /*InsnID*/0,
1256 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1265 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWrx,
1268 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // R3
[all …]
/external/llvm-project/llvm/test/TableGen/
DGlobalISelEmitterSubreg.td51 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
52 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegStat…
53 // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
54 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG,
56 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
58 // CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/1,
59 // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
60 // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Test::DRegsRegClassID,
61 // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Test::DRegsRegClassID
62 // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Test::SRegsRegClassID,
[all …]
DDefaultOpsGlobalISel.td37 // CHECK: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FMAX,
39 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // mod…
40 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
41 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // mod…
42 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
43 // CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/0,
44 // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
50 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FLOMP,
52 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
53 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // cla…
[all …]
DGlobalISelEmitterRegSequence.td44 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/MyTarget::SUBSOME_INSN,
45 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
47 // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
48 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/MyTarget::SUBSOME_INSN,
49 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
51 // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
52 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE,
54 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
55 // CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1,
56 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
[all …]
DGlobalISelEmitter-nested-subregs.td43 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
44 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
45 // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
47 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
48 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
50 // CHECK-NEXT: GIR_AddImm, /*InsnID*/1, /*Imm*/3,
51 // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, MyTarget::A0RegClassID,
52 // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, MyTarget::A0RegClassID,
53 // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, MyTarget::A0bRegClassID,
[all …]
DGlobalISelEmitter-input-discard.td20 // GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
21 // GISEL-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
22 // GISEL-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23 // GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FOO,
25 // GISEL-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
27 // GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0,
28 // GISEL-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
DGlobalISelEmitter.td281 // R19C-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1,
287 // R19C-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/MyTarget::INSN4,
288 // R19C-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
290 // R19C-NEXT: GIR_ComplexRenderer, /*InsnID*/1, /*RendererID*/1,
291 // R19C-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/2, /*SubOperand*/0, // s…
292 // R19C-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/2, /*SubOperand*/1, // s…
293 // R19C-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
294 // R19C-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::INSN3,
297 // R19C-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // s…
298 // R19C-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // s…
[all …]
Dgisel-physreg-input.td40 // GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
41 // GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, MyTarget::SPECIAL, /*AddRegisterRegFlags*/RegState::De…
43 // GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::ADD_PHYS,
46 // GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0,
47 // GISEL-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
68 // GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
69 // GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, MyTarget::SPECIAL, /*AddRegisterRegFlags*/RegState::De…
71 // GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MUL_PHYS,
74 // GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0,
75 // GISEL-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
DGlobalISelEmitterMatchTableOptimizer.td20 // CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::LOAD8,
21 // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30 // CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::LOAD32,
31 // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
61 // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1,
63 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::LOAD16Imm,
66 // CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOf…
67 // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
68 // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
75 // CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::LOAD16,
[all …]
DGlobalISelEmitter-zero-reg.td34 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::INST,
37 // CHECK-NEXT: GIR_AddRegister, /*InsnID*/0, MyTarget::NoRegister, /*AddRegisterRegFlags*/0,
38 // CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfLis…
39 // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
40 // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
DGlobalISelEmitter-output-discard.td17 // GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::ADD_CO,
19 // GISEL-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|R…
22 // GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0,
23 // GISEL-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
DGlobalISelEmitterVariadic.td34 // CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::ONE,
35 // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
48 // CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::TWO,
49 // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
DContextlessPredicates.td40 // CHECK_NOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::INS…
41 // CHECK_NOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
66 // CHECK_OPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::INSN,
67 // CHECK_OPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
DGlobalISelEmitterCustomPredicate.td77 // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1,
79 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::AND_OR,
107 // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1,
109 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::AND_OR,
151 // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1,
153 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::SUB3,
DGlobalISelEmitter-SDNodeXForm-timm.td24 // GISEL: GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GI…
33 // GISEL: GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*OperandRenderer*/GI…
DGlobalISelEmitter-immAllZeroOne.td33 // GISEL-NOOPT-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1,
48 // GISEL-NOOPT-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1,
DGlobalISelEmitter-atomic_store.td19 // GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::ST_ATOM_B32,
Dimmarg.td17 // GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::SLEEP0,
DGlobalISelEmitterOverloadedPtr.td22 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::ANYLOAD,
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenGlobalISel.inc867 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INC8r,
870 GIR_EraseFromParent, /*InsnID*/0,
871 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
879 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::DEC8r,
882 GIR_EraseFromParent, /*InsnID*/0,
883 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
892 GIM_CheckIsSafeToFold, /*InsnID*/1,
894 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD8ri,
898 GIR_EraseFromParent, /*InsnID*/0,
899 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenGlobalISel.inc755 GIM_CheckIsSafeToFold, /*InsnID*/1,
756 GIM_CheckIsSafeToFold, /*InsnID*/2,
758 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LSA,
763 GIR_EraseFromParent, /*InsnID*/0,
764 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
782 GIM_CheckIsSafeToFold, /*InsnID*/1,
783 GIM_CheckIsSafeToFold, /*InsnID*/2,
785 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LSA,
790 GIR_EraseFromParent, /*InsnID*/0,
791 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
[all …]
/external/llvm-project/llvm/utils/TableGen/
DGlobalISelEmitter.cpp2729 unsigned InsnID; member in __anon4852db4a0111::AddRegisterRenderer
2735 AddRegisterRenderer(unsigned InsnID, const CodeGenTarget &Target, in AddRegisterRenderer() argument
2737 : OperandRenderer(OR_Register), InsnID(InsnID), RegisterDef(RegisterDef), in AddRegisterRenderer()
2746 << MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID); in emitRenderOpcodes()
2774 unsigned InsnID; member in __anon4852db4a0111::TempRegRenderer
2781 TempRegRenderer(unsigned InsnID, unsigned TempRegID, bool IsDef = false, in TempRegRenderer() argument
2784 : OperandRenderer(OR_Register), InsnID(InsnID), TempRegID(TempRegID), in TempRegRenderer()
2798 Table << MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID) in emitRenderOpcodes()
2820 unsigned InsnID; member in __anon4852db4a0111::ImmRenderer
2824 ImmRenderer(unsigned InsnID, int64_t Imm) in ImmRenderer() argument
[all …]