1// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s 2 3include "llvm/Target/Target.td" 4include "GlobalISelEmitterCommon.td" 5 6// Boilerplate code for setting up some registers with subregs. 7class MyReg<string n, list<Register> subregs = []> 8 : Register<n> { 9 let SubRegs = subregs; 10} 11 12class MyClass<int size, list<ValueType> types, dag registers> 13 : RegisterClass<"Test", types, size, registers> { 14 let Size = size; 15} 16 17def sub0 : SubRegIndex<16>; 18def sub1 : SubRegIndex<16, 16>; 19def S0 : MyReg<"s0">; 20def S1 : MyReg<"s1">; 21def SRegs : MyClass<16, [i16], (sequence "S%u", 0, 1)>; 22 23let SubRegIndices = [sub0, sub1] in { 24def D0 : MyReg<"d0", [S0, S1]>; 25} 26 27def DRegs : MyClass<32, [i32], (sequence "D%u", 0, 0)>; 28def SOP : RegisterOperand<SRegs>; 29def DOP : RegisterOperand<DRegs>; 30def SOME_INSN : I<(outs DRegs:$dst), (ins DOP:$src), []>; 31def SUBSOME_INSN : I<(outs SRegs:$dst), (ins SOP:$src), []>; 32 33// CHECK: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, 34// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SEXT, 35// CHECK-NEXT: // MIs[0] dst 36// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 37// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Test::DRegsRegClassID, 38// CHECK-NEXT: // MIs[0] src 39// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 40// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Test::SRegsRegClassID, 41// CHECK-NEXT: // (sext:{ *:[i32] } SOP:{ *:[i16] }:$src) => (REG_SEQUENCE:{ *:[i32] } DRegs:{ *:[i32] }, (SUBSOME_INSN:{ *:[i16] } SOP:{ *:[i16] }:$src), sub0:{ *:[i32] }, (SUBSOME_INSN:{ *:[i16] } SOP:{ *:[i16] }:$src), sub1:{ *:[i32] }) 42// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, 43// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, 44// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/MyTarget::SUBSOME_INSN, 45// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 46// CHECK-NEXT: GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src 47// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 48// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/MyTarget::SUBSOME_INSN, 49// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 50// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 51// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 52// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE, 53// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 54// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 55// CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1, 56// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, 57// CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/2, 58// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, 59// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Test::DRegsRegClassID, 60// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Test::SRegsRegClassID, 61// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, Test::SRegsRegClassID, 62def : Pat<(i32 (sext SOP:$src)), 63 (REG_SEQUENCE DRegs, (SUBSOME_INSN SOP:$src), sub0, 64 (SUBSOME_INSN SOP:$src), sub1)>; 65 66 67// CHECK: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ZEXT, 68// CHECK: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::REG_SEQUENCE, 69// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 70// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 71// CHECK-NEXT: GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/1, 72// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 73// CHECK-NEXT: GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/2, 74// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, Test::DRegsRegClassID, 75// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, Test::SRegsRegClassID, 76// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, Test::SRegsRegClassID, 77// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::SOME_INSN, 78// Make sure operands are constrained when REG_SEQUENCE isn't the root instruction. 79def : Pat<(i32 (zext SOP:$src)), 80 (SOME_INSN (REG_SEQUENCE DRegs, (SUBSOME_INSN SOP:$src), sub0, 81 (SUBSOME_INSN SOP:$src), sub1))>; 82