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Searched refs:IsPlainRegister (Results 1 – 12 of 12) sorted by relevance

/external/vixl/test/aarch64/
Dtest-api-aarch64.cc983 VIXL_CHECK(Operand(x0).IsPlainRegister()); in TEST()
984 VIXL_CHECK(Operand(x1, LSL, 0).IsPlainRegister()); in TEST()
985 VIXL_CHECK(Operand(x2, LSR, 0).IsPlainRegister()); in TEST()
986 VIXL_CHECK(Operand(x3, ASR, 0).IsPlainRegister()); in TEST()
987 VIXL_CHECK(Operand(x4, ROR, 0).IsPlainRegister()); in TEST()
988 VIXL_CHECK(Operand(x5, UXTX).IsPlainRegister()); in TEST()
989 VIXL_CHECK(Operand(x6, SXTX).IsPlainRegister()); in TEST()
990 VIXL_CHECK(Operand(w7).IsPlainRegister()); in TEST()
991 VIXL_CHECK(Operand(w8, LSL, 0).IsPlainRegister()); in TEST()
992 VIXL_CHECK(Operand(w9, LSR, 0).IsPlainRegister()); in TEST()
[all …]
/external/vixl/src/aarch64/
Doperands-aarch64.cc191 bool Operand::IsPlainRegister() const { in IsPlainRegister() function in vixl::aarch64::Operand
336 bool MemOperand::IsPlainRegister() const { in IsPlainRegister() function in vixl::aarch64::MemOperand
425 bool SVEMemOperand::IsPlainRegister() const { in IsPlainRegister() function in vixl::aarch64::SVEMemOperand
Doperands-aarch64.h326 bool IsPlainRegister() const;
426 bool IsPlainRegister() const;
577 bool IsPlainRegister() const;
Dmacro-assembler-aarch64.cc1300 if (!left.IsPlainRegister()) { in CselHelper()
1308 if (!right.IsPlainRegister()) { in CselHelper()
1317 VIXL_ASSERT(left.IsPlainRegister() && right.IsPlainRegister()); in CselHelper()
1401 if (left.IsPlainRegister()) { in CselSubHelperRightSmallImmediate()
Dassembler-sve-aarch64.cc4820 VIXL_ASSERT(addr.IsPlainRegister() || in VIXL_SVE_LOAD_STORE_SIGNED_VARIANT_LIST()
4836 VIXL_ASSERT(addr.IsPlainRegister() || in ldnf1d()
4852 VIXL_ASSERT(addr.IsPlainRegister() || in ldnf1h()
4868 VIXL_ASSERT(addr.IsPlainRegister() || in ldnf1sb()
4884 VIXL_ASSERT(addr.IsPlainRegister() || in ldnf1sh()
4900 VIXL_ASSERT(addr.IsPlainRegister() || in ldnf1sw()
4916 VIXL_ASSERT(addr.IsPlainRegister() || in ldnf1w()
Dmacro-assembler-sve-aarch64.cc843 VIXL_ASSERT(op.IsPlainRegister()); in Index()
/external/vixl/src/aarch32/
Doperands-aarch32.cc533 } else if (operand.IsPlainRegister()) { in operator <<()
553 if (operand.IsPlainRegister()) { in operator <<()
Dmacro-assembler-aarch32.h1001 operand.IsPlainRegister() && rn.IsLow() && rd.Is(rn) && in Adc()
1023 rn.Is(rd) && operand.IsPlainRegister() && in Adc()
1078 (operand.IsPlainRegister() && rd.IsLow() && rn.IsLow() && in Add()
1081 (operand.IsPlainRegister() && !rd.IsPC() && rn.Is(rd) && in Add()
1085 (operand.IsPlainRegister() && !rd.IsPC() && rn.IsSP() && in Add()
1108 ((operand.IsPlainRegister() && rd.IsLow() && rn.IsLow() && in Add()
1159 if (rd.Is(rn) && operand.IsPlainRegister() && in And()
1175 operand.IsPlainRegister() && rd.Is(rn) && rn.IsLow() && in And()
1196 if (operand.IsPlainRegister() && rd.Is(rn) && in And()
1201 rn.Is(rd) && operand.IsPlainRegister() && in And()
[all …]
Doperands-aarch32.h144 bool IsPlainRegister() const { in IsPlainRegister() function
808 bool IsPlainRegister() const { in IsPlainRegister() function
Dassembler-aarch32.cc1957 if (operand.IsPlainRegister()) { in adc()
2045 if (operand.IsPlainRegister()) { in adcs()
2218 if (operand.IsPlainRegister()) { in add()
2330 if (operand.IsPlainRegister()) { in add()
2412 if (operand.IsPlainRegister()) { in adds()
2729 if (operand.IsPlainRegister()) { in and_()
2817 if (operand.IsPlainRegister()) { in ands()
2909 if (operand.IsPlainRegister()) { in asr()
2978 if (operand.IsPlainRegister()) { in asrs()
3284 if (operand.IsPlainRegister()) { in bic()
[all …]
Dmacro-assembler-aarch32.cc1793 } else if (operand.IsPlainRegister()) { in Delegate()
2020 if (operand.IsPlainRegister()) { in Delegate()
Ddisasm-aarch32.h479 } else if (operand.IsPlainRegister()) {
503 if (operand.IsPlainRegister()) {