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Searched refs:LD_B (Results 1 – 25 of 38) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/ARM/ParallelDSP/
Dexchange.ll7 ; CHECK: [[LD_B:%[^ ]+]] = load i32, i32* [[CAST_B]]
8 ; CHECK: call i32 @llvm.arm.smladx(i32 [[LD_A]], i32 [[LD_B]]
32 ; CHECK: [[LD_B:%[^ ]+]] = load i32, i32* [[CAST_B]]
33 ; CHECK: call i32 @llvm.arm.smladx(i32 [[LD_A]], i32 [[LD_B]]
57 ; CHECK: [[LD_B:%[^ ]+]] = load i32, i32* [[CAST_B]]
58 ; CHECK: call i32 @llvm.arm.smladx(i32 [[LD_B]], i32 [[LD_A]]
82 ; CHECK: [[LD_B:%[^ ]+]] = load i32, i32* [[CAST_B]]
83 ; CHECK: call i32 @llvm.arm.smladx(i32 [[LD_B]], i32 [[LD_A]]
107 ; CHECK: [[LD_B:%[^ ]+]] = load i32, i32* [[CAST_B]]
108 ; CHECK: [[X:%[^ ]+]] = call i32 @llvm.arm.smladx(i32 [[LD_A]], i32 [[LD_B]], i32 %acc
[all …]
Doverlapping.ll9 ; CHECK: [[LD_B:%[^ ]+]] = load i32, i32* [[CAST_B]]
10 ; CHECK: [[ACC:%[^ ]+]] = call i32 @llvm.arm.smlad(i32 [[LD_A]], i32 [[LD_B]], i32 %acc)
53 ; CHECK: [[LD_B:%[^ ]+]] = load i32, i32* [[CAST_B]]
54 ; CHECK: [[ACC:%[^ ]+]] = call i64 @llvm.arm.smlald(i32 [[LD_A]], i32 [[LD_B]], i64 %acc)
97 ; CHECK: [[LD_B:%[^ ]+]] = load i32, i32* [[CAST_B]]
100 ; CHECK: [[RES:%[^ ]+]] = call i32 @llvm.arm.smlad(i32 [[LD_A]], i32 [[LD_B]], i32 [[ACC2]])
135 ; CHECK: [[LD_B:%[^ ]+]] = load i32, i32* [[CAST_B]]
136 ; CHECK: [[SMLAD:%[^ ]+]] = call i32 @llvm.arm.smlad(i32 [[LD_A]], i32 [[LD_B]], i32 %acc)
181 ; CHECK: [[LD_B:%[^ ]+]] = load i32, i32* [[CAST_B]]
182 ; CHECK: [[SMLAD:%[^ ]+]] = call i32 @llvm.arm.smlad(i32 [[LD_A]], i32 [[LD_B]], i32 %acc)
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
Drem_and_div_vec.mir41 ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load 16 from %ir.a)
42 ; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load 16 from %ir.b)
43 ; P5600: [[DIV_S_B:%[0-9]+]]:msa128b = DIV_S_B [[LD_B]], [[LD_B1]]
161 ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load 16 from %ir.a)
162 ; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load 16 from %ir.b)
163 ; P5600: [[MOD_S_B:%[0-9]+]]:msa128b = MOD_S_B [[LD_B]], [[LD_B1]]
281 ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load 16 from %ir.a)
282 ; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load 16 from %ir.b)
283 ; P5600: [[DIV_U_B:%[0-9]+]]:msa128b = DIV_U_B [[LD_B]], [[LD_B1]]
401 ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load 16 from %ir.a)
[all …]
Dsub_vec.mir26 ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load 16 from %ir.a)
27 ; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load 16 from %ir.b)
28 ; P5600: [[SUBV_B:%[0-9]+]]:msa128b = SUBV_B [[LD_B1]], [[LD_B]]
Dmul_vec.mir26 ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load 16 from %ir.a)
27 ; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load 16 from %ir.b)
28 ; P5600: [[MULV_B:%[0-9]+]]:msa128b = MULV_B [[LD_B1]], [[LD_B]]
Dadd_vec.mir26 ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load 16 from %ir.a)
27 ; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load 16 from %ir.b)
28 ; P5600: [[ADDV_B:%[0-9]+]]:msa128b = ADDV_B [[LD_B1]], [[LD_B]]
Dload_store_vec.mir27 ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load 16 from %ir.b)
28 ; P5600: ST_B [[LD_B]], [[COPY]], 0 :: (store 16 into %ir.a)
/external/libyuv/files/include/libyuv/
Dmacros_msa.h140 #define LD_B(RTYPE, psrc) *((RTYPE*)(psrc)) /* NOLINT */ macro
141 #define LD_UB(...) LD_B(const v16u8, __VA_ARGS__)
158 out0 = LD_B(RTYPE, (psrc)); \
159 out1 = LD_B(RTYPE, (psrc) + stride); \
/external/libvpx/libvpx/third_party/libyuv/include/libyuv/
Dmacros_msa.h140 #define LD_B(RTYPE, psrc) *((RTYPE*)(psrc)) /* NOLINT */ macro
141 #define LD_UB(...) LD_B(const v16u8, __VA_ARGS__)
158 out0 = LD_B(RTYPE, (psrc)); \
159 out1 = LD_B(RTYPE, (psrc) + stride); \
/external/llvm-project/llvm/test/CodeGen/Mips/msa/
Demergency-spill.mir138 $w0 = LD_B %stack.1.a, 0 :: (dereferenceable load 16 from %ir.a)
141 $w1 = LD_B %stack.2.b, 0 :: (dereferenceable load 16 from %ir.b)
178 $w0 = LD_B %stack.3.a.addr, 0 :: (dereferenceable load 16 from %ir.a.addr)
212 $w1 = LD_B %stack.4.b.addr, 0 :: (dereferenceable load 16 from %ir.b.addr)
215 $w0 = LD_B %stack.4.b.addr, 0 :: (dereferenceable load 16 from %ir.b.addr)
/external/llvm/lib/Target/Mips/
DMipsSERegisterInfo.cpp68 case Mips::LD_B: in getLoadStoreOffsetSizeInBits()
DMipsSEInstrInfo.cpp284 Opc = Mips::LD_B; in loadRegFromStack()
/external/libpng/mips/
Dfilter_msa_intrinsics.c251 #define LD_B(RTYPE, psrc) *((RTYPE *) (psrc)) macro
252 #define LD_UB(...) LD_B(v16u8, __VA_ARGS__)
255 out0 = LD_B(RTYPE, (psrc)); \
256 out1 = LD_B(RTYPE, (psrc) + stride); \
/external/libvpx/libvpx/vp8/common/mips/msa/
Dvp8_macros_msa.h19 #define LD_B(RTYPE, psrc) *((const RTYPE *)(psrc)) macro
20 #define LD_UB(...) LD_B(v16u8, __VA_ARGS__)
21 #define LD_SB(...) LD_B(v16i8, __VA_ARGS__)
270 out0 = LD_B(RTYPE, (psrc)); \
271 out1 = LD_B(RTYPE, (psrc) + stride); \
279 out2 = LD_B(RTYPE, (psrc) + 2 * stride); \
295 out4 = LD_B(RTYPE, (psrc) + 4 * stride); \
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsSERegisterInfo.cpp68 case Mips::LD_B: in getLoadStoreOffsetSizeInBits()
DMipsInstructionSelector.cpp235 return isStore ? Mips::ST_B : Mips::LD_B; in selectLoadStoreOpCode()
DMipsSEInstrInfo.cpp351 Opc = Mips::LD_B; in loadRegFromStack()
/external/llvm-project/llvm/lib/Target/Mips/
DMipsSERegisterInfo.cpp68 case Mips::LD_B: in getLoadStoreOffsetSizeInBits()
DMipsInstructionSelector.cpp241 return isStore ? Mips::ST_B : Mips::LD_B; in selectLoadStoreOpCode()
DMipsSEInstrInfo.cpp351 Opc = Mips::LD_B; in loadRegFromStack()
/external/webp/src/dsp/
Dmsa_macro.h48 #define LD_B(RTYPE, psrc) *((RTYPE*)(psrc)) macro
49 #define LD_UB(...) LD_B(v16u8, __VA_ARGS__)
50 #define LD_SB(...) LD_B(v16i8, __VA_ARGS__)
221 out0 = LD_B(RTYPE, psrc); \
222 out1 = LD_B(RTYPE, psrc + stride); \
229 out2 = LD_B(RTYPE, psrc + 2 * stride); \
/external/libaom/libaom/aom_dsp/mips/
Dmacros_msa.h21 #define LD_B(RTYPE, psrc) *((const RTYPE *)(psrc)) macro
22 #define LD_UB(...) LD_B(v16u8, __VA_ARGS__)
23 #define LD_SB(...) LD_B(v16i8, __VA_ARGS__)
297 out0 = LD_B(RTYPE, (psrc)); \
298 out1 = LD_B(RTYPE, (psrc) + stride); \
306 out2 = LD_B(RTYPE, (psrc) + 2 * stride); \
321 out4 = LD_B(RTYPE, (psrc) + 4 * stride); \
/external/llvm-project/llvm/test/Transforms/LowerMatrixIntrinsics/
Dmultiply-fused.ll16 ; CHECK-NEXT: [[LD_B:%.*]] = ptrtoint <16 x double>* [[A:%.*]] to i64
17 ; CHECK-NEXT: [[TMP0:%.*]] = icmp ugt i64 [[ST_E]], [[LD_B]]
20 ; CHECK-NEXT: [[LD_E:%.*]] = add nuw nsw i64 [[LD_B]], 128
Dmultiply-fused-multiple-blocks.ll27 ; CHECK-NEXT: [[LD_B:%.*]] = ptrtoint <6 x double>* [[A]] to i64
28 ; CHECK-NEXT: [[TMP0:%.*]] = icmp ugt i64 [[ST_E]], [[LD_B]]
31 ; CHECK-NEXT: [[LD_E:%.*]] = add nuw nsw i64 [[LD_B]], 48
/external/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp1486 case Mips::LD_B: in DecodeMSA128Mem()

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