1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600 3--- | 4 5 define void @mul_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void } 6 define void @mul_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void } 7 define void @mul_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void } 8 define void @mul_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void } 9 10... 11--- 12name: mul_v16i8 13alignment: 4 14legalized: true 15regBankSelected: true 16tracksRegLiveness: true 17body: | 18 bb.1.entry: 19 liveins: $a0, $a1, $a2 20 21 ; P5600-LABEL: name: mul_v16i8 22 ; P5600: liveins: $a0, $a1, $a2 23 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 24 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 25 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2 26 ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load 16 from %ir.a) 27 ; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load 16 from %ir.b) 28 ; P5600: [[MULV_B:%[0-9]+]]:msa128b = MULV_B [[LD_B1]], [[LD_B]] 29 ; P5600: ST_B [[MULV_B]], [[COPY2]], 0 :: (store 16 into %ir.c) 30 ; P5600: RetRA 31 %0:gprb(p0) = COPY $a0 32 %1:gprb(p0) = COPY $a1 33 %2:gprb(p0) = COPY $a2 34 %3:fprb(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.a) 35 %4:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.b) 36 %5:fprb(<16 x s8>) = G_MUL %4, %3 37 G_STORE %5(<16 x s8>), %2(p0) :: (store 16 into %ir.c) 38 RetRA 39 40... 41--- 42name: mul_v8i16 43alignment: 4 44legalized: true 45regBankSelected: true 46tracksRegLiveness: true 47body: | 48 bb.1.entry: 49 liveins: $a0, $a1, $a2 50 51 ; P5600-LABEL: name: mul_v8i16 52 ; P5600: liveins: $a0, $a1, $a2 53 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 54 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 55 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2 56 ; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY]], 0 :: (load 16 from %ir.a) 57 ; P5600: [[LD_H1:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load 16 from %ir.b) 58 ; P5600: [[MULV_H:%[0-9]+]]:msa128h = MULV_H [[LD_H1]], [[LD_H]] 59 ; P5600: ST_H [[MULV_H]], [[COPY2]], 0 :: (store 16 into %ir.c) 60 ; P5600: RetRA 61 %0:gprb(p0) = COPY $a0 62 %1:gprb(p0) = COPY $a1 63 %2:gprb(p0) = COPY $a2 64 %3:fprb(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.a) 65 %4:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.b) 66 %5:fprb(<8 x s16>) = G_MUL %4, %3 67 G_STORE %5(<8 x s16>), %2(p0) :: (store 16 into %ir.c) 68 RetRA 69 70... 71--- 72name: mul_v4i32 73alignment: 4 74legalized: true 75regBankSelected: true 76tracksRegLiveness: true 77body: | 78 bb.1.entry: 79 liveins: $a0, $a1, $a2 80 81 ; P5600-LABEL: name: mul_v4i32 82 ; P5600: liveins: $a0, $a1, $a2 83 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 84 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 85 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2 86 ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load 16 from %ir.a) 87 ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load 16 from %ir.b) 88 ; P5600: [[MULV_W:%[0-9]+]]:msa128w = MULV_W [[LD_W1]], [[LD_W]] 89 ; P5600: ST_W [[MULV_W]], [[COPY2]], 0 :: (store 16 into %ir.c) 90 ; P5600: RetRA 91 %0:gprb(p0) = COPY $a0 92 %1:gprb(p0) = COPY $a1 93 %2:gprb(p0) = COPY $a2 94 %3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a) 95 %4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b) 96 %5:fprb(<4 x s32>) = G_MUL %4, %3 97 G_STORE %5(<4 x s32>), %2(p0) :: (store 16 into %ir.c) 98 RetRA 99 100... 101--- 102name: mul_v2i64 103alignment: 4 104legalized: true 105regBankSelected: true 106tracksRegLiveness: true 107body: | 108 bb.1.entry: 109 liveins: $a0, $a1, $a2 110 111 ; P5600-LABEL: name: mul_v2i64 112 ; P5600: liveins: $a0, $a1, $a2 113 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 114 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 115 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2 116 ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load 16 from %ir.a) 117 ; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load 16 from %ir.b) 118 ; P5600: [[MULV_D:%[0-9]+]]:msa128d = MULV_D [[LD_D1]], [[LD_D]] 119 ; P5600: ST_D [[MULV_D]], [[COPY2]], 0 :: (store 16 into %ir.c) 120 ; P5600: RetRA 121 %0:gprb(p0) = COPY $a0 122 %1:gprb(p0) = COPY $a1 123 %2:gprb(p0) = COPY $a2 124 %3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a) 125 %4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b) 126 %5:fprb(<2 x s64>) = G_MUL %4, %3 127 G_STORE %5(<2 x s64>), %2(p0) :: (store 16 into %ir.c) 128 RetRA 129 130... 131