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Searched refs:LaneIdx (Results 1 – 22 of 22) sorted by relevance

/external/llvm-project/llvm/lib/Target/AArch64/GISel/
DAArch64PostLegalizerLowering.cpp559 auto LaneIdx = getSplatIndex(MI); in matchDupLane() local
560 if (!LaneIdx) in matchDupLane()
564 if (*LaneIdx >= SrcTy.getNumElements()) in matchDupLane()
598 MatchInfo.second = *LaneIdx; in matchDupLane()
DAArch64InstructionSelector.cpp138 Register EltReg, unsigned LaneIdx,
241 Register VecReg, unsigned LaneIdx,
2419 unsigned LaneIdx = Offset / 64; in select() local
2422 DstReg, DstRB, LLT::scalar(64), SrcReg, LaneIdx, MIB); in select()
3668 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const { in emitExtractVectorElt() argument
3699 if (LaneIdx == 0) { in emitExtractVectorElt()
3718 MIRBuilder.buildInstr(CopyOpc, {*DstReg}, {InsertReg}).addImm(LaneIdx); in emitExtractVectorElt()
3752 unsigned LaneIdx = VRegAndVal->Value; in selectExtractElt() local
3758 LaneIdx, MIRBuilder); in selectExtractElt()
3885 unsigned LaneIdx = 1; in selectUnmergeValues() local
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstructionSelector.cpp111 Register EltReg, unsigned LaneIdx,
153 Register VecReg, unsigned LaneIdx,
1704 unsigned LaneIdx = Offset / 64; in select() local
1707 DstReg, DstRB, LLT::scalar(64), SrcReg, LaneIdx, MIB); in select()
2902 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const { in emitExtractVectorElt() argument
2933 if (LaneIdx == 0) { in emitExtractVectorElt()
2952 MIRBuilder.buildInstr(CopyOpc, {*DstReg}, {InsertReg}).addImm(LaneIdx); in emitExtractVectorElt()
2986 unsigned LaneIdx = VRegAndVal->Value; in selectExtractElt() local
2992 LaneIdx, MIRBuilder); in selectExtractElt()
3119 unsigned LaneIdx = 1; in selectUnmergeValues() local
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DAArch64ISelDAGToDAG.cpp539 static bool checkHighLaneIndex(SDNode *DL, SDValue &LaneOp, int &LaneIdx) { in checkHighLaneIndex() argument
554 LaneIdx = DLidx->getSExtValue() + EVidx->getSExtValue(); in checkHighLaneIndex()
563 SDValue &LaneOp, int &LaneIdx) { in checkV64LaneV128() argument
565 if (!checkHighLaneIndex(Op0.getNode(), LaneOp, LaneIdx)) { in checkV64LaneV128()
567 if (!checkHighLaneIndex(Op0.getNode(), LaneOp, LaneIdx)) in checkV64LaneV128()
583 int LaneIdx = -1; // Will hold the lane index. in tryMLAV64LaneV128() local
587 LaneIdx)) { in tryMLAV64LaneV128()
591 LaneIdx)) in tryMLAV64LaneV128()
595 SDValue LaneIdxVal = CurDAG->getTargetConstant(LaneIdx, dl, MVT::i64); in tryMLAV64LaneV128()
626 int LaneIdx; in tryMULLV64LaneV128() local
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DAArch64ISelLowering.cpp8079 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64); in LowerBUILD_VECTOR() local
8083 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx); in LowerBUILD_VECTOR()
8138 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64); in LowerBUILD_VECTOR() local
8139 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx); in LowerBUILD_VECTOR()
/external/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp419 static bool checkHighLaneIndex(SDNode *DL, SDValue &LaneOp, int &LaneIdx) { in checkHighLaneIndex() argument
434 LaneIdx = DLidx->getSExtValue() + EVidx->getSExtValue(); in checkHighLaneIndex()
443 SDValue &LaneOp, int &LaneIdx) { in checkV64LaneV128() argument
445 if (!checkHighLaneIndex(Op0.getNode(), LaneOp, LaneIdx)) { in checkV64LaneV128()
447 if (!checkHighLaneIndex(Op0.getNode(), LaneOp, LaneIdx)) in checkV64LaneV128()
463 int LaneIdx = -1; // Will hold the lane index. in tryMLAV64LaneV128() local
467 LaneIdx)) { in tryMLAV64LaneV128()
471 LaneIdx)) in tryMLAV64LaneV128()
475 SDValue LaneIdxVal = CurDAG->getTargetConstant(LaneIdx, dl, MVT::i64); in tryMLAV64LaneV128()
506 int LaneIdx; in tryMULLV64LaneV128() local
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DAArch64ISelLowering.cpp6383 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64); in LowerBUILD_VECTOR() local
6387 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx); in LowerBUILD_VECTOR()
6435 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64); in LowerBUILD_VECTOR() local
6436 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx); in LowerBUILD_VECTOR()
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp599 static bool checkHighLaneIndex(SDNode *DL, SDValue &LaneOp, int &LaneIdx) { in checkHighLaneIndex() argument
614 LaneIdx = DLidx->getSExtValue() + EVidx->getSExtValue(); in checkHighLaneIndex()
623 SDValue &LaneOp, int &LaneIdx) { in checkV64LaneV128() argument
625 if (!checkHighLaneIndex(Op0.getNode(), LaneOp, LaneIdx)) { in checkV64LaneV128()
627 if (!checkHighLaneIndex(Op0.getNode(), LaneOp, LaneIdx)) in checkV64LaneV128()
643 int LaneIdx = -1; // Will hold the lane index. in tryMLAV64LaneV128() local
647 LaneIdx)) { in tryMLAV64LaneV128()
651 LaneIdx)) in tryMLAV64LaneV128()
655 SDValue LaneIdxVal = CurDAG->getTargetConstant(LaneIdx, dl, MVT::i64); in tryMLAV64LaneV128()
686 int LaneIdx; in tryMULLV64LaneV128() local
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DAArch64ISelLowering.cpp9578 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64); in LowerBUILD_VECTOR() local
9582 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx); in LowerBUILD_VECTOR()
9653 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64); in LowerBUILD_VECTOR() local
9654 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx); in LowerBUILD_VECTOR()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/InstCombine/
DInstCombineSimplifyDemanded.cpp1695 unsigned LaneIdx = Lane * VWidthPerLane; in SimplifyDemandedVectorElts() local
1697 unsigned Idx = LaneIdx + Elt + InnerVWidthPerLane * OpNum; in SimplifyDemandedVectorElts()
/external/llvm-project/llvm/lib/Target/X86/
DX86InstCombineIntrinsic.cpp1960 unsigned LaneIdx = Lane * VWidthPerLane; in simplifyDemandedVectorEltsIntrinsic() local
1962 unsigned Idx = LaneIdx + Elt + InnerVWidthPerLane * OpNum; in simplifyDemandedVectorEltsIntrinsic()
DX86ISelLowering.cpp6858 int LaneIdx = (Idx / NumEltsPerLane) * NumEltsPerLane; in getHorizDemandedElts() local
6861 DemandedLHS.setBit(LaneIdx + 2 * LocalIdx + 0); in getHorizDemandedElts()
6862 DemandedLHS.setBit(LaneIdx + 2 * LocalIdx + 1); in getHorizDemandedElts()
6865 DemandedRHS.setBit(LaneIdx + 2 * LocalIdx + 0); in getHorizDemandedElts()
6866 DemandedRHS.setBit(LaneIdx + 2 * LocalIdx + 1); in getHorizDemandedElts()
21513 unsigned LaneIdx = LExtIndex / NumEltsPerLane; in lowerAddSubToHorizontalOp() local
21514 X = extract128BitVector(X, LaneIdx * NumEltsPerLane, DAG, DL); in lowerAddSubToHorizontalOp()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/
DAMDGPUAsmParser.cpp5513 int64_t LaneIdx; in parseSwizzleBroadcast() local
5524 if (parseSwizzleOperands(1, &LaneIdx, in parseSwizzleBroadcast()
5527 Imm = encodeBitmaskPerm(BITMASK_MAX - GroupSize + 1, LaneIdx, 0); in parseSwizzleBroadcast()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrSIMD.td36 def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">;
/external/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
DAMDGPUAsmParser.cpp6300 int64_t LaneIdx; in parseSwizzleBroadcast() local
6312 if (parseSwizzleOperand(LaneIdx, in parseSwizzleBroadcast()
6316 Imm = encodeBitmaskPerm(BITMASK_MAX - GroupSize + 1, LaneIdx, 0); in parseSwizzleBroadcast()
/external/llvm-project/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrSIMD.td38 def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">;
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp5845 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i32); in LowerBUILD_VECTOR() local
5846 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx); in LowerBUILD_VECTOR()
9803 SDValue LaneIdx = DAG.getConstant(Idx, dl, MVT::i32); in PerformARMBUILD_VECTORCombine() local
9804 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecVT, Vec, V, LaneIdx); in PerformARMBUILD_VECTORCombine()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMISelLowering.cpp7376 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i32); in LowerBUILD_VECTOR() local
7377 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx); in LowerBUILD_VECTOR()
12929 SDValue LaneIdx = DAG.getConstant(Idx, dl, MVT::i32); in PerformARMBUILD_VECTORCombine() local
12930 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecVT, Vec, V, LaneIdx); in PerformARMBUILD_VECTORCombine()
/external/llvm-project/llvm/lib/Target/ARM/
DARMISelLowering.cpp7680 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i32); in LowerBUILD_VECTOR() local
7681 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx); in LowerBUILD_VECTOR()
13828 SDValue LaneIdx = DAG.getConstant(Idx, dl, MVT::i32); in PerformARMBUILD_VECTORCombine() local
13829 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecVT, Vec, V, LaneIdx); in PerformARMBUILD_VECTORCombine()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86ISelLowering.cpp6573 int LaneIdx = (Idx / NumEltsPerLane) * NumEltsPerLane; in getHorizDemandedElts() local
6576 DemandedLHS.setBit(LaneIdx + 2 * LocalIdx + 0); in getHorizDemandedElts()
6577 DemandedLHS.setBit(LaneIdx + 2 * LocalIdx + 1); in getHorizDemandedElts()
6580 DemandedRHS.setBit(LaneIdx + 2 * LocalIdx + 0); in getHorizDemandedElts()
6581 DemandedRHS.setBit(LaneIdx + 2 * LocalIdx + 1); in getHorizDemandedElts()
20394 unsigned LaneIdx = LExtIndex / NumEltsPerLane; in lowerAddSubToHorizontalOp() local
20395 X = extract128BitVector(X, LaneIdx * NumEltsPerLane, DAG, DL); in lowerAddSubToHorizontalOp()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp7738 int LaneIdx = (Mask[l + i] % NumElts) - l; in lowerVectorShuffleAsByteRotate() local
7740 if (LaneIdx < 0 || LaneIdx >= NumLaneElts) in lowerVectorShuffleAsByteRotate()
7744 int StartIdx = i - LaneIdx; in lowerVectorShuffleAsByteRotate()
/external/llvm-project/clang/lib/CodeGen/
DCGBuiltin.cpp17048 Value *LaneIdx = llvm::ConstantInt::get(getLLVMContext(), *LaneIdxConst); in EmitWebAssemblyBuiltinExpr() local
17079 return Builder.CreateCall(Callee, {Ptr, Vec, LaneIdx}); in EmitWebAssemblyBuiltinExpr()