| /external/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCTargetDesc.cpp | 145 unsigned llvm::HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes) { in HexagonConvertUnits() argument
157 return (*Lanes = 4, CVI_XLANE); in HexagonConvertUnits()
160 return (*Lanes = 2, CVI_XLANE | CVI_MPY0); in HexagonConvertUnits()
162 return (*Lanes = 2, CVI_MPY0); in HexagonConvertUnits()
164 return (*Lanes = 2, CVI_XLANE); in HexagonConvertUnits()
169 return (*Lanes = 1, CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1); in HexagonConvertUnits()
172 return (*Lanes = 1, CVI_XLANE | CVI_SHIFT); in HexagonConvertUnits()
175 return (*Lanes = 1, CVI_MPY0 | CVI_MPY1); in HexagonConvertUnits()
177 return (*Lanes = 1, CVI_ZW); in HexagonConvertUnits()
179 return (*Lanes = 1, CVI_XLANE); in HexagonConvertUnits()
[all …]
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| D | HexagonShuffler.cpp | 115 unsigned Lanes; in HexagonCVIResource() local
116 const unsigned Units = HexagonConvertUnits(ItinUnits, &Lanes); in HexagonCVIResource()
118 if (Units == 0 && Lanes == 0) { in HexagonCVIResource()
129 setLanes(Lanes); in HexagonCVIResource()
137 unsigned Lanes; member
141 static unsigned makeAllBits(unsigned startBit, unsigned Lanes) in makeAllBits() argument
143 for (unsigned i = 1; i < Lanes; ++i) in makeAllBits()
156 unsigned allBits = makeAllBits(b, hvxInsts[startIdx].Lanes); in checkHVXPipes()
336 inst.Lanes = I->CVI.getLanes(); in ValidResourceUsage()
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| D | HexagonShuffler.h | 86 unsigned Lanes; variable
92 void setLanes(unsigned l) { Lanes = l; } in setLanes()
102 unsigned getLanes() const { return Lanes; } in getLanes()
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| D | HexagonMCTargetDesc.h | 100 unsigned HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes);
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonShuffler.h | 74 unsigned Lanes; variable
80 void setLanes(unsigned l) { Lanes = l; }; in setLanes()
90 unsigned getLanes() const { return (Lanes); }; in getLanes()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonShuffler.h | 82 unsigned Lanes; variable
88 void setLanes(unsigned l) { Lanes = l; } in setLanes()
99 unsigned getLanes() const { return Lanes; } in getLanes()
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| D | HexagonShuffler.cpp | 169 unsigned Lanes; member
173 static unsigned makeAllBits(unsigned startBit, unsigned Lanes) in makeAllBits() argument
175 for (unsigned i = 1; i < Lanes; ++i) in makeAllBits()
188 unsigned allBits = makeAllBits(b, hvxInsts[startIdx].Lanes); in checkHVXPipes()
601 inst.Lanes = I->CVI.getLanes(); in check()
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| /external/llvm-project/clang/utils/TableGen/ |
| D | MveEmitter.cpp | 290 unsigned Lanes; member in __anonf88c1dfe0111::VectorType
293 VectorType(const ScalarType *Element, unsigned Lanes) in VectorType() argument
294 : CRegularNamedType(TypeKind::Vector), Element(Element), Lanes(Lanes) {} in VectorType()
295 unsigned sizeInBits() const override { return Lanes * Element->sizeInBits(); } in sizeInBits()
296 unsigned lanes() const { return Lanes; } in lanes()
300 return Element->cNameBase() + "x" + utostr(Lanes); in cNameBase()
304 utostr(Lanes) + ")"; in llvmName()
342 unsigned Lanes; member in __anonf88c1dfe0111::PredicateType
345 PredicateType(unsigned Lanes) in PredicateType() argument
346 : CRegularNamedType(TypeKind::Predicate), Lanes(Lanes) {} in PredicateType()
[all …]
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| /external/rust/crates/ppv-lite86/src/ |
| D | types.rs | 199 pub trait MultiLane<Lanes> {
201 fn to_lanes(self) -> Lanes; in to_lanes() argument
203 fn from_lanes(lanes: Lanes) -> Self; in from_lanes()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | MVETailPredication.cpp | 284 unsigned Lanes = cast<VectorType>(Insert->getType())->getNumElements(); in isTailPredicate() local
287 if (!match(InLoop, m_Add(m_Instruction(LHS), m_SpecificInt(Lanes)))) in isTailPredicate()
307 unsigned Lanes = VecTy->getNumElements(); in IsPredicatedVectorLoop() local
312 if (Lanes * ElementWidth > MaxWidth || Lanes == MaxWidth) in IsPredicatedVectorLoop()
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| /external/arm-trusted-firmware/docs/plat/ |
| D | ls1043a.rst | 29 * PCIe2 (Lanes C) to mini-PCIe slot
30 * PCIe3 (Lanes D) to PCIe slot
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIMachineFunctionInfo.cpp | 335 if (!Spill.Lanes.empty()) in allocateVGPRSpillToAGPR()
340 Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister); in allocateVGPRSpillToAGPR()
382 Spill.Lanes[I] = *NextSpillReg++; in allocateVGPRSpillToAGPR()
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| D | SIMachineFunctionInfo.h | 454 SmallVector<MCPhysReg, 32> Lanes;
512 : I->second.Lanes[Lane];
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIMachineFunctionInfo.cpp | 381 if (!Spill.Lanes.empty()) in allocateVGPRSpillToAGPR()
386 Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister); in allocateVGPRSpillToAGPR()
428 Spill.Lanes[I] = *NextSpillReg++; in allocateVGPRSpillToAGPR()
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| D | SIMachineFunctionInfo.h | 465 SmallVector<MCPhysReg, 32> Lanes;
536 : I->second.Lanes[Lane];
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| /external/llvm/include/llvm/IR/ |
| D | IntrinsicsAArch64.td | 160 // Vector Add Across Lanes
165 // Vector Long Add Across Lanes
256 // Vector Max Across Lanes
272 // Vector Min Across Lanes
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| /external/llvm-project/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 1563 const size_t Lanes = Op.getNumOperands(); in LowerBUILD_VECTOR() local
1632 for (size_t I = 0; I < Lanes; ++I) { in LowerBUILD_VECTOR()
1697 size_t LaneBits = 128 / Lanes; in LowerBUILD_VECTOR()
1698 size_t HalfLanes = Lanes / 2; in LowerBUILD_VECTOR()
1699 for (size_t I = 0; I < Lanes; ++I) { in LowerBUILD_VECTOR()
1761 for (size_t I = 0; I < Lanes; ++I) { in LowerBUILD_VECTOR()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | IntrinsicsAArch64.td | 177 // Vector Add Across Lanes
182 // Vector Long Add Across Lanes
273 // Vector Max Across Lanes
289 // Vector Min Across Lanes
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 744 int Lanes = 1; in getCastInstrCost() local
746 Lanes = SrcTy.getVectorNumElements(); in getCastInstrCost()
749 return Lanes; in getCastInstrCost()
751 return Lanes * CallCost; in getCastInstrCost()
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| /external/llvm/lib/CodeGen/ |
| D | RegisterCoalescer.cpp | 1995 LaneBitmask Lanes = SubRangeJoin ? 1 : TRI->getSubRegIndexLaneMask(SubIdx); in analyzeValue() local
1996 V.ValidLanes = V.WriteLanes = Lanes; in analyzeValue()
2297 LaneBitmask Lanes) const { in usesLanes()
2305 if (Lanes & TRI->getSubRegIndexLaneMask( in usesLanes()
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| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | O3-pipeline.ll | 105 ; CHECK-NEXT: Detect Dead Lanes
|
| /external/llvm-project/llvm/include/llvm/IR/ |
| D | IntrinsicsAArch64.td | 196 // Vector Add Across Lanes
201 // Vector Long Add Across Lanes
296 // Vector Max Across Lanes
312 // Vector Min Across Lanes
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 1313 const size_t Lanes = Op.getNumOperands(); in LowerBUILD_VECTOR() local
1382 for (size_t I = 0; I < Lanes; ++I) { in LowerBUILD_VECTOR()
1460 for (size_t I = 0; I < Lanes; ++I) { in LowerBUILD_VECTOR()
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| /external/llvm-project/llvm/test/CodeGen/X86/ |
| D | opt-pipeline.ll | 121 ; CHECK-NEXT: Detect Dead Lanes
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| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | O3-pipeline.ll | 136 ; CHECK-NEXT: Detect Dead Lanes
|