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Searched refs:MASK0 (Results 1 – 12 of 12) sorted by relevance

/external/lua/src/
Dlopcodes.h108 #define MASK0(n,p) (~MASK1(n,p)) macro
115 #define SET_OPCODE(i,o) ((i) = (((i)&MASK0(SIZE_OP,POS_OP)) | \
122 #define setarg(i,v,pos,size) ((i) = (((i)&MASK0(size,pos)) | \
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dwave32.ll234 ; GFX1032: s_or_b32 [[MASK0:s[0-9]+]], [[MASK0]], vcc_lo
235 ; GFX1064: s_or_b64 [[MASK0:s\[[0-9:]+\]]], [[MASK0]], vcc
239 ; GFX1032: s_and_b32 [[MASK0]], [[MASK0]], exec_lo
240 ; GFX1064: s_and_b64 [[MASK0]], [[MASK0]], exec
241 ; GFX1032: s_or_b32 [[MASK1]], [[MASK1]], [[MASK0]]
242 ; GFX1064: s_or_b64 [[MASK1]], [[MASK1]], [[MASK0]]
/external/llvm-project/llvm/test/Instrumentation/HeapProfiler/
Dmasked-load-store.ll76 ; STORE: [[MASK0:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 0
77 ; STORE: br i1 [[MASK0]], label %[[THEN0:[0-9A-Za-z]+]], label %[[AFTER0:[0-9A-Za-z]+]]
190 ; LOAD: [[MASK0:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 0
191 ; LOAD: br i1 [[MASK0]], label %[[THEN0:[0-9A-Za-z]+]], label %[[AFTER0:[0-9A-Za-z]+]]
/external/llvm-project/llvm/test/Instrumentation/AddressSanitizer/
Dasan-masked-load-store.ll84 ; STORE: [[MASK0:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 0
85 ; STORE: br i1 [[MASK0]], label %[[THEN0:[0-9A-Za-z]+]], label %[[AFTER0:[0-9A-Za-z]+]]
212 ; LOAD: [[MASK0:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 0
213 ; LOAD: br i1 [[MASK0]], label %[[THEN0:[0-9A-Za-z]+]], label %[[AFTER0:[0-9A-Za-z]+]]
/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/
Dcore_sc300.h831 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ member
Dcore_cm3.h849 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ member
Dcore_cm4.h910 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ member
Dcore_cm7.h1112 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ member
/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/
Dcore_cm3.h849 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ member
Dcore_sc300.h831 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ member
Dcore_cm4.h910 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ member
Dcore_cm7.h1112 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ member