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Searched refs:MCPhysReg (Results 1 – 25 of 484) sorted by relevance

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/external/llvm-project/llvm/unittests/CodeGen/
DAllocationOrderTest.cpp15 std::vector<MCPhysReg> loadOrder(const AllocationOrder &O, unsigned Limit = 0) { in loadOrder()
16 std::vector<MCPhysReg> Ret; in loadOrder()
28 SmallVector<MCPhysReg, 16> Hints = {1, 2, 3}; in TEST()
29 SmallVector<MCPhysReg, 16> Order = {4, 5, 6, 7}; in TEST()
31 EXPECT_EQ((std::vector<MCPhysReg>{1, 2, 3, 4, 5, 6, 7}), loadOrder(O)); in TEST()
35 SmallVector<MCPhysReg, 16> Hints = {1, 2, 3}; in TEST()
36 SmallVector<MCPhysReg, 16> Order = {4, 1, 5, 6}; in TEST()
38 EXPECT_EQ((std::vector<MCPhysReg>{1, 2, 3, 4, 5, 6}), loadOrder(O)); in TEST()
42 SmallVector<MCPhysReg, 16> Hints = {1, 2, 3}; in TEST()
43 SmallVector<MCPhysReg, 16> Order = {4, 5, 6, 7}; in TEST()
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/external/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCMCTargetDesc.h158 using llvm::MCPhysReg;
161 static const MCPhysReg RRegs[32] = PPC_REGS0_31(PPC::R); \
162 static const MCPhysReg XRegs[32] = PPC_REGS0_31(PPC::X); \
163 static const MCPhysReg FRegs[32] = PPC_REGS0_31(PPC::F); \
164 static const MCPhysReg VSRpRegs[32] = PPC_REGS0_31(PPC::VSRp); \
165 static const MCPhysReg SPERegs[32] = PPC_REGS0_31(PPC::S); \
166 static const MCPhysReg VFRegs[32] = PPC_REGS0_31(PPC::VF); \
167 static const MCPhysReg VRegs[32] = PPC_REGS0_31(PPC::V); \
168 static const MCPhysReg RRegsNoR0[32] = \
170 static const MCPhysReg XRegsNoX0[32] = \
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCMCTargetDesc.h156 using llvm::MCPhysReg;
159 static const MCPhysReg RRegs[32] = PPC_REGS0_31(PPC::R); \
160 static const MCPhysReg XRegs[32] = PPC_REGS0_31(PPC::X); \
161 static const MCPhysReg FRegs[32] = PPC_REGS0_31(PPC::F); \
162 static const MCPhysReg SPERegs[32] = PPC_REGS0_31(PPC::S); \
163 static const MCPhysReg VFRegs[32] = PPC_REGS0_31(PPC::VF); \
164 static const MCPhysReg VRegs[32] = PPC_REGS0_31(PPC::V); \
165 static const MCPhysReg QFRegs[32] = PPC_REGS0_31(PPC::QF); \
166 static const MCPhysReg RRegsNoR0[32] = \
168 static const MCPhysReg XRegsNoX0[32] = \
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/external/capstone/arch/X86/
DX86GenRegisterInfo.inc350 static const MCPhysReg X86RegDiffLists[] = {
654 static const MCPhysReg GR8[] = {
664 static const MCPhysReg GR8_NOREX[] = {
674 static const MCPhysReg VK1[] = {
684 static const MCPhysReg VK2[] = {
694 static const MCPhysReg VK4[] = {
704 static const MCPhysReg VK8[] = {
714 static const MCPhysReg VK1WM[] = {
724 static const MCPhysReg VK2WM[] = {
734 static const MCPhysReg VK4WM[] = {
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/external/capstone/arch/ARM/
DARMGenRegisterInfo.inc492 static const MCPhysReg ARMRegDiffLists[] = {
1180 static MCPhysReg SPR[] = {
1190 static MCPhysReg GPR[] = {
1200 static MCPhysReg GPRwithAPSR[] = {
1210 static MCPhysReg SPR_8[] = {
1220 static MCPhysReg GPRnopc[] = {
1230 static MCPhysReg rGPR[] = {
1240 static MCPhysReg hGPR[] = {
1250 static MCPhysReg tGPR[] = {
1260 static MCPhysReg GPRnopc_and_hGPR[] = {
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/external/llvm-project/llvm/include/llvm/CodeGen/
DCallingConvLower.h168 ForwardedRegister(Register VReg, MCPhysReg PReg, MVT VT) in ForwardedRegister()
171 MCPhysReg PReg;
336 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated()
343 void DeallocateReg(MCPhysReg Reg) { in DeallocateReg()
351 MCRegister AllocateReg(MCPhysReg Reg) { in AllocateReg()
359 MCRegister AllocateReg(MCPhysReg Reg, MCPhysReg ShadowReg) { in AllocateReg()
370 MCPhysReg AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg()
376 MCPhysReg Reg = Regs[FirstUnalloc]; in AllocateReg()
384 MCPhysReg AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) { in AllocateRegBlock()
411 MCRegister AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg()
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DLivePhysRegs.h50 using RegisterSet = SparseSet<MCPhysReg, identity<MCPhysReg>>;
79 void addReg(MCPhysReg Reg) { in addReg()
89 void removeReg(MCPhysReg Reg) { in removeReg()
98 SmallVectorImpl<std::pair<MCPhysReg, const MachineOperand*>> *Clobbers =
106 bool contains(MCPhysReg Reg) const { return LiveRegs.count(Reg); } in contains()
109 bool available(const MachineRegisterInfo &MRI, MCPhysReg Reg) const;
129 SmallVectorImpl<std::pair<MCPhysReg, const MachineOperand*>> &Clobbers);
DRegisterClassInfo.h37 std::unique_ptr<MCPhysReg[]> Order;
41 operator ArrayRef<MCPhysReg>() const {
59 const MCPhysReg *CalleeSavedRegs = nullptr;
62 SmallVector<MCPhysReg, 4> CalleeSavedAliases;
96 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DLivePhysRegs.h50 using RegisterSet = SparseSet<MCPhysReg, identity<MCPhysReg>>;
79 void addReg(MCPhysReg Reg) { in addReg()
89 void removeReg(MCPhysReg Reg) { in removeReg()
98 SmallVectorImpl<std::pair<MCPhysReg, const MachineOperand*>> *Clobbers =
106 bool contains(MCPhysReg Reg) const { return LiveRegs.count(Reg); } in contains()
109 bool available(const MachineRegisterInfo &MRI, MCPhysReg Reg) const;
129 SmallVectorImpl<std::pair<MCPhysReg, const MachineOperand*>> &Clobbers);
DRegisterClassInfo.h37 std::unique_ptr<MCPhysReg[]> Order;
41 operator ArrayRef<MCPhysReg>() const {
59 const MCPhysReg *CalleeSavedRegs = nullptr;
62 SmallVector<MCPhysReg, 4> CalleeSavedAliases;
96 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
/external/llvm-project/llvm/lib/CodeGen/
DRegAllocFast.cpp91 MCPhysReg PhysReg = 0; ///< Currently held here.
148 void setPhysRegState(MCPhysReg PhysReg, unsigned NewState);
149 bool isPhysRegFree(MCPhysReg PhysReg) const;
152 void markRegUsedInInstr(MCPhysReg PhysReg) { in markRegUsedInInstr()
158 bool isRegUsedInInstr(MCPhysReg PhysReg, bool LookAtPhysRegUses) const { in isRegUsedInInstr()
170 void markPhysRegUsedInInstr(MCPhysReg PhysReg) { in markPhysRegUsedInInstr()
176 void unmarkRegUsedInInstr(MCPhysReg PhysReg) { in unmarkRegUsedInInstr()
221 bool usePhysReg(MachineInstr &MI, MCPhysReg PhysReg);
222 bool definePhysReg(MachineInstr &MI, MCPhysReg PhysReg);
223 bool displacePhysReg(MachineInstr &MI, MCPhysReg PhysReg);
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DAllocationOrder.h31 const SmallVector<MCPhysReg, 16> Hints;
32 ArrayRef<MCPhysReg> Order;
90 AllocationOrder(SmallVector<MCPhysReg, 16> &&Hints, ArrayRef<MCPhysReg> Order, in AllocationOrder() argument
111 ArrayRef<MCPhysReg> getOrder() const { return Order; } in getOrder()
117 static_cast<uint32_t>(std::numeric_limits<MCPhysReg>::max())); in isHint()
/external/capstone/
DMCRegisterInfo.c25 const MCPhysReg *List;
33 const MCPhysReg *DL, in MCRegisterInfo_InitMCRegisterInfo()
53 static void DiffListIterator_init(DiffListIterator *d, MCPhysReg InitVal, const MCPhysReg *DiffList) in DiffListIterator_init()
66 MCPhysReg D; in DiffListIterator_next()
94 DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SuperRegs); in MCRegisterInfo_getMatchingSuperReg()
113 DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SubRegs); in MCRegisterInfo_getSubReg()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMCallingConv.cpp24 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS()
67 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64AssignAAPCS()
68 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64AssignAAPCS()
69 static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 }; in f64AssignAAPCS()
70 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS()
119 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64RetAssign()
120 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64RetAssign()
156 static const MCPhysReg RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
158 static const MCPhysReg SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3,
162 static const MCPhysReg DRegList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3,
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/external/llvm/lib/Target/ARM/
DARMCallingConv.h31 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS()
74 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64AssignAAPCS()
75 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64AssignAAPCS()
76 static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 }; in f64AssignAAPCS()
77 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS()
126 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64RetAssign()
127 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64RetAssign()
163 static const MCPhysReg RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
165 static const MCPhysReg SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3,
169 static const MCPhysReg DRegList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3,
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/external/llvm-project/llvm/tools/llvm-exegesis/lib/
DMCInstrDescView.cpp131 for (const MCPhysReg *MCPhysReg = Description->getImplicitDefs(); in create() local
132 MCPhysReg && *MCPhysReg; ++MCPhysReg, ++OpIndex) { in create()
136 Operand.Tracker = &RATC.getRegister(*MCPhysReg); in create()
137 Operand.ImplicitReg = MCPhysReg; in create()
140 for (const MCPhysReg *MCPhysReg = Description->getImplicitUses(); in create() local
141 MCPhysReg && *MCPhysReg; ++MCPhysReg, ++OpIndex) { in create()
145 Operand.Tracker = &RATC.getRegister(*MCPhysReg); in create()
146 Operand.ImplicitReg = MCPhysReg; in create()
326 addOperandIfAlias(const MCPhysReg Reg, bool SelectDef, in addOperandIfAlias()
358 for (const MCPhysReg Reg : CommonRegisters.set_bits()) { in AliasingConfigurations()
/external/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.cpp55 const MCPhysReg *
60 static const MCPhysReg Int32[] = { in getCallerSavedRegs()
63 static const MCPhysReg Int64[] = { in getCallerSavedRegs()
66 static const MCPhysReg Pred[] = { in getCallerSavedRegs()
69 static const MCPhysReg VecSgl[] = { in getCallerSavedRegs()
74 static const MCPhysReg VecDbl[] = { in getCallerSavedRegs()
95 static const MCPhysReg Empty[] = { 0 }; in getCallerSavedRegs()
104 const MCPhysReg *
106 static const MCPhysReg CalleeSavedRegsV3[] = { in getCalleeSavedRegs()
114 static const MCPhysReg CalleeSavedRegsV3EHReturn[] = { in getCalleeSavedRegs()
/external/llvm-project/llvm/lib/Target/ARM/
DARMCallingConv.cpp24 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS()
65 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64AssignAAPCS()
66 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64AssignAAPCS()
67 static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 }; in f64AssignAAPCS()
68 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS()
116 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64RetAssign()
117 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64RetAssign()
153 static const MCPhysReg RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
155 static const MCPhysReg SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3,
159 static const MCPhysReg DRegList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3,
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/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenCallingConv.inc89 static const MCPhysReg RegList1[] = {
92 static const MCPhysReg RegList2[] = {
158 static const MCPhysReg RegList3[] = {
185 static const MCPhysReg RegList4[] = {
215 static const MCPhysReg RegList5[] = {
218 static const MCPhysReg RegList6[] = {
229 static const MCPhysReg RegList7[] = {
232 static const MCPhysReg RegList8[] = {
244 static const MCPhysReg ShadowRegList9[] = {
254 static const MCPhysReg RegList11[] = {
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/external/capstone/arch/Mips/
DMipsGenRegisterInfo.inc497 static MCPhysReg MipsRegDiffLists[] = {
995 static MCPhysReg OddSP[] = {
1005 static MCPhysReg CCR[] = {
1015 static MCPhysReg COP2[] = {
1025 static MCPhysReg COP3[] = {
1035 static MCPhysReg DSPR[] = {
1045 static MCPhysReg FGR32[] = {
1055 static MCPhysReg FGRCC[] = {
1065 static MCPhysReg FGRH32[] = {
1075 static MCPhysReg GPR32[] = {
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/external/capstone/arch/SystemZ/
DSystemZGenRegisterInfo.inc252 static const MCPhysReg SystemZRegDiffLists[] = {
508 static const MCPhysReg GRX32Bit[] = {
518 static const MCPhysReg VR32Bit[] = {
528 static const MCPhysReg AR32Bit[] = {
538 static const MCPhysReg FP32Bit[] = {
548 static const MCPhysReg GR32Bit[] = {
558 static const MCPhysReg GRH32Bit[] = {
568 static const MCPhysReg ADDR32Bit[] = {
578 static const MCPhysReg CCR[] = {
588 static const MCPhysReg AnyRegBit[] = {
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/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/
DMCRegisterInfo.h33 using iterator = const MCPhysReg*;
34 using const_iterator = const MCPhysReg*;
156 const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table.
157 const MCPhysReg *DiffLists; // Pointer to the difflists array
191 const MCPhysReg *List = nullptr;
200 void init(MCPhysReg InitVal, const MCPhysReg *DiffList) { in init()
210 MCPhysReg D = *List++; in advance()
236 std::forward_iterator_tag, MCPhysReg> {
239 MCPhysReg Val;
245 mc_difflist_iterator(MCRegister Reg, const MCPhysReg *DiffList) { in mc_difflist_iterator()
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/external/llvm-project/llvm/include/llvm/MC/
DMCRegisterInfo.h33 using iterator = const MCPhysReg*;
34 using const_iterator = const MCPhysReg*;
156 const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table.
157 const MCPhysReg *DiffLists; // Pointer to the difflists array
191 const MCPhysReg *List = nullptr;
200 void init(MCPhysReg InitVal, const MCPhysReg *DiffList) { in init()
210 MCPhysReg D = *List++; in advance()
236 std::forward_iterator_tag, MCPhysReg> {
239 MCPhysReg Val;
245 mc_difflist_iterator(MCRegister Reg, const MCPhysReg *DiffList) { in mc_difflist_iterator()
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/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCCallingConv.cpp36 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_AlignArgRegs()
61 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
86 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
114 static const MCPhysReg HiRegList[] = { PPC::R3, PPC::R5, PPC::R7, PPC::R9 }; in CC_PPC32_SPE_CustomSplitFP64()
115 static const MCPhysReg LoRegList[] = { PPC::R4, PPC::R6, PPC::R8, PPC::R10 }; in CC_PPC32_SPE_CustomSplitFP64()
143 static const MCPhysReg HiRegList[] = { PPC::R3 }; in CC_PPC32_SPE_RetF64()
144 static const MCPhysReg LoRegList[] = { PPC::R4 }; in CC_PPC32_SPE_RetF64()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCCallingConv.cpp36 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_AlignArgRegs()
61 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
86 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
114 static const MCPhysReg HiRegList[] = { PPC::R3, PPC::R5, PPC::R7, PPC::R9 }; in CC_PPC32_SPE_CustomSplitFP64()
115 static const MCPhysReg LoRegList[] = { PPC::R4, PPC::R6, PPC::R8, PPC::R10 }; in CC_PPC32_SPE_CustomSplitFP64()
143 static const MCPhysReg HiRegList[] = { PPC::R3 }; in CC_PPC32_SPE_RetF64()
144 static const MCPhysReg LoRegList[] = { PPC::R4 }; in CC_PPC32_SPE_RetF64()

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