1 //===-- PPCMCTargetDesc.h - PowerPC Target Descriptions ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides PowerPC specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H
14 #define LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H
15
16 // GCC #defines PPC on Linux but we use it as our namespace name
17 #undef PPC
18
19 #include "llvm/MC/MCRegisterInfo.h"
20 #include "llvm/Support/MathExtras.h"
21 #include <cstdint>
22 #include <memory>
23
24 namespace llvm {
25
26 class MCAsmBackend;
27 class MCCodeEmitter;
28 class MCContext;
29 class MCInstrInfo;
30 class MCObjectTargetWriter;
31 class MCRegisterInfo;
32 class MCSubtargetInfo;
33 class MCTargetOptions;
34 class Target;
35 class Triple;
36 class StringRef;
37 class raw_pwrite_stream;
38
39 MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII,
40 const MCRegisterInfo &MRI,
41 MCContext &Ctx);
42
43 MCAsmBackend *createPPCAsmBackend(const Target &T, const MCSubtargetInfo &STI,
44 const MCRegisterInfo &MRI,
45 const MCTargetOptions &Options);
46
47 /// Construct an PPC ELF object writer.
48 std::unique_ptr<MCObjectTargetWriter> createPPCELFObjectWriter(bool Is64Bit,
49 uint8_t OSABI);
50 /// Construct a PPC Mach-O object writer.
51 std::unique_ptr<MCObjectTargetWriter>
52 createPPCMachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype);
53
54 /// Construct a PPC XCOFF object writer.
55 std::unique_ptr<MCObjectTargetWriter> createPPCXCOFFObjectWriter(bool Is64Bit);
56
57 /// Returns true iff Val consists of one contiguous run of 1s with any number of
58 /// 0s on either side. The 1s are allowed to wrap from LSB to MSB, so
59 /// 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is not,
60 /// since all 1s are not contiguous.
isRunOfOnes(unsigned Val,unsigned & MB,unsigned & ME)61 static inline bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
62 if (!Val)
63 return false;
64
65 if (isShiftedMask_32(Val)) {
66 // look for the first non-zero bit
67 MB = countLeadingZeros(Val);
68 // look for the first zero bit after the run of ones
69 ME = countLeadingZeros((Val - 1) ^ Val);
70 return true;
71 } else {
72 Val = ~Val; // invert mask
73 if (isShiftedMask_32(Val)) {
74 // effectively look for the first zero bit
75 ME = countLeadingZeros(Val) - 1;
76 // effectively look for the first one bit after the run of zeros
77 MB = countLeadingZeros((Val - 1) ^ Val) + 1;
78 return true;
79 }
80 }
81 // no run present
82 return false;
83 }
84
isRunOfOnes64(uint64_t Val,unsigned & MB,unsigned & ME)85 static inline bool isRunOfOnes64(uint64_t Val, unsigned &MB, unsigned &ME) {
86 if (!Val)
87 return false;
88
89 if (isShiftedMask_64(Val)) {
90 // look for the first non-zero bit
91 MB = countLeadingZeros(Val);
92 // look for the first zero bit after the run of ones
93 ME = countLeadingZeros((Val - 1) ^ Val);
94 return true;
95 } else {
96 Val = ~Val; // invert mask
97 if (isShiftedMask_64(Val)) {
98 // effectively look for the first zero bit
99 ME = countLeadingZeros(Val) - 1;
100 // effectively look for the first one bit after the run of zeros
101 MB = countLeadingZeros((Val - 1) ^ Val) + 1;
102 return true;
103 }
104 }
105 // no run present
106 return false;
107 }
108
109 } // end namespace llvm
110
111 // Generated files will use "namespace PPC". To avoid symbol clash,
112 // undefine PPC here. PPC may be predefined on some hosts.
113 #undef PPC
114
115 // Defines symbolic names for PowerPC registers. This defines a mapping from
116 // register name to register number.
117 //
118 #define GET_REGINFO_ENUM
119 #include "PPCGenRegisterInfo.inc"
120
121 // Defines symbolic names for the PowerPC instructions.
122 //
123 #define GET_INSTRINFO_ENUM
124 #define GET_INSTRINFO_SCHED_ENUM
125 #include "PPCGenInstrInfo.inc"
126
127 #define GET_SUBTARGETINFO_ENUM
128 #include "PPCGenSubtargetInfo.inc"
129
130 #define PPC_REGS0_31(X) \
131 { \
132 X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \
133 X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \
134 X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \
135 }
136
137 #define PPC_REGS_NO0_31(Z, X) \
138 { \
139 Z, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \
140 X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \
141 X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \
142 }
143
144 #define PPC_REGS_LO_HI(LO, HI) \
145 { \
146 LO##0, LO##1, LO##2, LO##3, LO##4, LO##5, LO##6, LO##7, LO##8, LO##9, \
147 LO##10, LO##11, LO##12, LO##13, LO##14, LO##15, LO##16, LO##17, \
148 LO##18, LO##19, LO##20, LO##21, LO##22, LO##23, LO##24, LO##25, \
149 LO##26, LO##27, LO##28, LO##29, LO##30, LO##31, HI##0, HI##1, HI##2, \
150 HI##3, HI##4, HI##5, HI##6, HI##7, HI##8, HI##9, HI##10, HI##11, \
151 HI##12, HI##13, HI##14, HI##15, HI##16, HI##17, HI##18, HI##19, \
152 HI##20, HI##21, HI##22, HI##23, HI##24, HI##25, HI##26, HI##27, \
153 HI##28, HI##29, HI##30, HI##31 \
154 }
155
156 using llvm::MCPhysReg;
157
158 #define DEFINE_PPC_REGCLASSES \
159 static const MCPhysReg RRegs[32] = PPC_REGS0_31(PPC::R); \
160 static const MCPhysReg XRegs[32] = PPC_REGS0_31(PPC::X); \
161 static const MCPhysReg FRegs[32] = PPC_REGS0_31(PPC::F); \
162 static const MCPhysReg SPERegs[32] = PPC_REGS0_31(PPC::S); \
163 static const MCPhysReg VFRegs[32] = PPC_REGS0_31(PPC::VF); \
164 static const MCPhysReg VRegs[32] = PPC_REGS0_31(PPC::V); \
165 static const MCPhysReg QFRegs[32] = PPC_REGS0_31(PPC::QF); \
166 static const MCPhysReg RRegsNoR0[32] = \
167 PPC_REGS_NO0_31(PPC::ZERO, PPC::R); \
168 static const MCPhysReg XRegsNoX0[32] = \
169 PPC_REGS_NO0_31(PPC::ZERO8, PPC::X); \
170 static const MCPhysReg VSRegs[64] = \
171 PPC_REGS_LO_HI(PPC::VSL, PPC::V); \
172 static const MCPhysReg VSFRegs[64] = \
173 PPC_REGS_LO_HI(PPC::F, PPC::VF); \
174 static const MCPhysReg VSSRegs[64] = \
175 PPC_REGS_LO_HI(PPC::F, PPC::VF); \
176 static const MCPhysReg CRBITRegs[32] = { \
177 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, \
178 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, \
179 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, \
180 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, \
181 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, \
182 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, \
183 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, \
184 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN}; \
185 static const MCPhysReg CRRegs[8] = { \
186 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, \
187 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7}
188
189 #endif // LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H
190