Home
last modified time | relevance | path

Searched refs:MCUCFG_REG (Results 1 – 2 of 2) sorted by relevance

/external/arm-trusted-firmware/plat/mediatek/mt8192/include/
Dmcucfg.h16 #define MCUCFG_REG(ofs) (uint32_t)(MCUCFG_BASE + (ofs)) macro
18 #define MP2_MISC_CONFIG_BOOT_ADDR_L(cpu) (MCUCFG_REG(0x2290) + ((cpu) * 8))
19 #define MP2_MISC_CONFIG_BOOT_ADDR_H(cpu) (MCUCFG_REG(0x2294) + ((cpu) * 8))
21 #define MP2_CPUCFG MCUCFG_REG(0x2208)
26 #define MP0_CPUTOP_SPMC_CTL MCUCFG_REG(0x788)
27 #define MP1_CPUTOP_SPMC_CTL MCUCFG_REG(0x78C)
28 #define MP1_CPUTOP_SPMC_SRAM_CTL MCUCFG_REG(0x790)
53 (MCUCFG_REG(0x1c30) + cluster * 0x2000 + cpu * 4)
55 #define CPUSYS0_CPU0_SPMC_CTL MCUCFG_REG(0x1c30)
56 #define CPUSYS0_CPU1_SPMC_CTL MCUCFG_REG(0x1c34)
[all …]
/external/arm-trusted-firmware/plat/mediatek/mt8192/drivers/spmc/
Dmtspmc_private.h33 #define MCUCFG_REG(ofs) (uint32_t)(MCUCFG_BASE + (ofs)) macro
68 #define SPM_MCUSYS_PWR_CON MCUCFG_REG(0xd200)
69 #define SPM_MP0_CPUTOP_PWR_CON MCUCFG_REG(0xd204)
70 #define SPM_MP0_CPU0_PWR_CON MCUCFG_REG(0xd208)
71 #define SPM_MP0_CPU1_PWR_CON MCUCFG_REG(0xd20c)
72 #define SPM_MP0_CPU2_PWR_CON MCUCFG_REG(0xd210)
73 #define SPM_MP0_CPU3_PWR_CON MCUCFG_REG(0xd214)
74 #define SPM_MP0_CPU4_PWR_CON MCUCFG_REG(0xd218)
75 #define SPM_MP0_CPU5_PWR_CON MCUCFG_REG(0xd21c)
76 #define SPM_MP0_CPU6_PWR_CON MCUCFG_REG(0xd220)
[all …]