| /external/arm-trusted-firmware/plat/arm/common/ |
| D | arm_common.c | 93 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1; in arm_get_spsr_for_bl33_entry()
207 assert((client_mode == MODE_EL2) || (client_mode == MODE_EL1)); in plat_sdei_validate_entry_point()
208 if (client_mode == MODE_EL2) { in plat_sdei_validate_entry_point()
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| /external/arm-trusted-firmware/plat/arm/common/aarch64/ |
| D | execution_state_switch.c | 93 from_el2 = caller_64 ? (GET_EL(spsr) == MODE_EL2) : in arm_execution_state_switch()
138 el = from_el2 ? MODE_EL2 : MODE_EL1; in arm_execution_state_switch()
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| /external/arm-trusted-firmware/plat/intel/soc/common/aarch64/ |
| D | platform_common.c | 50 mode = (el_status) ? MODE_EL2 : MODE_EL1; in socfpga_get_spsr_for_bl33_entry()
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| /external/arm-trusted-firmware/plat/brcm/common/ |
| D | brcm_common.c | 45 mode = el_implemented(2) ? MODE_EL2 : MODE_EL1; in brcm_get_spsr_for_bl33_entry()
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| /external/arm-trusted-firmware/plat/nvidia/tegra/soc/t132/ |
| D | plat_sip_calls.c | 31 #define SPSR64 SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS)
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| /external/arm-trusted-firmware/plat/common/aarch64/ |
| D | plat_common.c | 74 } else if (el == MODE_EL2) { in get_el_str()
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| /external/arm-trusted-firmware/bl1/aarch64/ |
| D | bl1_context_mgmt.c | 78 mode = MODE_EL2; in bl1_prepare_next_image()
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| /external/arm-trusted-firmware/plat/marvell/armada/common/aarch64/ |
| D | marvell_common.c | 118 mode = (el_status) ? MODE_EL2 : MODE_EL1; in marvell_get_spsr_for_bl33_entry()
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| /external/arm-trusted-firmware/plat/renesas/common/ |
| D | bl2_plat_mem_params_desc.c | 21 #define BL33_MODE MODE_EL2
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| /external/arm-trusted-firmware/plat/xilinx/versal/ |
| D | bl31_versal_setup.c | 52 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, in bl31_set_default_config()
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| /external/arm-trusted-firmware/plat/layerscape/common/ |
| D | ls_common.c | 153 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1; in ls_get_spsr_for_bl33_entry()
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| /external/arm-trusted-firmware/plat/socionext/uniphier/ |
| D | uniphier_image_desc.c | 89 .ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
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| /external/arm-trusted-firmware/plat/allwinner/common/ |
| D | sunxi_bl31_setup.c | 100 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, in bl31_early_platform_setup2()
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| /external/arm-trusted-firmware/lib/el3_runtime/aarch64/ |
| D | context_mgmt.c | 194 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) in cm_setup_context()
210 if ((security_state == SECURE) && (GET_EL(ep->spsr) == MODE_EL2)) { in cm_setup_context()
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| /external/arm-trusted-firmware/plat/imx/imx8m/imx8mm/ |
| D | imx8mm_bl31_setup.c | 71 mode = (el_status) ? MODE_EL2 : MODE_EL1; in get_spsr_for_bl33_entry()
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| /external/arm-trusted-firmware/plat/imx/imx8m/imx8mp/ |
| D | imx8mp_bl31_setup.c | 69 mode = (el_status) ? MODE_EL2 : MODE_EL1; in get_spsr_for_bl33_entry()
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| /external/arm-trusted-firmware/plat/hisilicon/poplar/ |
| D | bl2_plat_setup.c | 68 mode = (el_status) ? MODE_EL2 : MODE_EL1; in poplar_get_spsr_for_bl33_entry()
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| /external/arm-trusted-firmware/plat/imx/imx8m/imx8mn/ |
| D | imx8mn_bl31_setup.c | 71 mode = (el_status) ? MODE_EL2 : MODE_EL1; in get_spsr_for_bl33_entry()
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| /external/arm-trusted-firmware/plat/intel/soc/stratix10/ |
| D | bl2_plat_setup.c | 144 mode = (el_status) ? MODE_EL2 : MODE_EL1; in get_spsr_for_bl33_entry()
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| /external/arm-trusted-firmware/plat/intel/soc/agilex/ |
| D | bl2_plat_setup.c | 148 mode = (el_status) ? MODE_EL2 : MODE_EL1; in get_spsr_for_bl33_entry()
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| /external/arm-trusted-firmware/services/std_svc/spmd/ |
| D | spmd_main.c | 216 SPMD_SPM_AT_SEL2 ? MODE_EL2 : MODE_EL1); in spmd_spmc_init()
274 static const uint32_t runtime_el = MODE_EL2; in spmd_spmc_init()
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| /external/arm-trusted-firmware/plat/arm/board/arm_fpga/ |
| D | fpga_bl31_setup.c | 36 return SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); in fpga_get_spsr_for_bl33_entry()
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| /external/arm-trusted-firmware/plat/socionext/synquacer/ |
| D | sq_bl31_setup.c | 58 mode = (el_status) ? MODE_EL2 : MODE_EL1; in sq_get_spsr_for_bl33_entry()
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| /external/arm-trusted-firmware/plat/qemu/common/ |
| D | qemu_bl2_setup.c | 127 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1; in qemu_get_spsr_for_bl33_entry()
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| /external/arm-trusted-firmware/plat/xilinx/zynqmp/ |
| D | bl31_zynqmp_setup.c | 51 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, in bl31_set_default_config()
|