1 /*
2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <arch.h>
12 #include <arch_helpers.h>
13 #include <common/bl_common.h>
14 #include <common/debug.h>
15 #include <drivers/arm/pl011.h>
16 #include <lib/mmio.h>
17 #include <sq_common.h>
18
19 static console_t console;
20 static entry_point_info_t bl32_image_ep_info;
21 static entry_point_info_t bl33_image_ep_info;
22
23 IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_START__, SPM_SHIM_EXCEPTIONS_START);
24 IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_END__, SPM_SHIM_EXCEPTIONS_END);
25 IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_LMA__, SPM_SHIM_EXCEPTIONS_LMA);
26
bl31_plat_get_next_image_ep_info(uint32_t type)27 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
28 {
29 assert(sec_state_is_valid(type));
30 return type == NON_SECURE ? &bl33_image_ep_info : &bl32_image_ep_info;
31 }
32
33 /*******************************************************************************
34 * Gets SPSR for BL32 entry
35 ******************************************************************************/
sq_get_spsr_for_bl32_entry(void)36 uint32_t sq_get_spsr_for_bl32_entry(void)
37 {
38 /*
39 * The Secure Payload Dispatcher service is responsible for
40 * setting the SPSR prior to entry into the BL32 image.
41 */
42 return 0;
43 }
44
45 /*******************************************************************************
46 * Gets SPSR for BL33 entry
47 ******************************************************************************/
sq_get_spsr_for_bl33_entry(void)48 uint32_t sq_get_spsr_for_bl33_entry(void)
49 {
50 unsigned long el_status;
51 unsigned int mode;
52 uint32_t spsr;
53
54 /* Figure out what mode we enter the non-secure world in */
55 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
56 el_status &= ID_AA64PFR0_ELX_MASK;
57
58 mode = (el_status) ? MODE_EL2 : MODE_EL1;
59
60 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
61 return spsr;
62 }
63
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)64 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
65 u_register_t arg2, u_register_t arg3)
66 {
67 /* Initialize the console to provide early debug support */
68 (void)console_pl011_register(PLAT_SQ_BOOT_UART_BASE,
69 PLAT_SQ_BOOT_UART_CLK_IN_HZ,
70 SQ_CONSOLE_BAUDRATE, &console);
71
72 console_set_scope(&console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME);
73
74 /* There are no parameters from BL2 if BL31 is a reset vector */
75 assert(arg0 == 0U);
76 assert(arg1 == 0U);
77
78 /* Initialize power controller before setting up topology */
79 plat_sq_pwrc_setup();
80
81 #ifdef SPD_opteed
82 struct draminfo di = {0};
83
84 sq_scp_get_draminfo(&di);
85
86 /*
87 * Check if OP-TEE has been loaded in Secure RAM allocated
88 * from DRAM1 region
89 */
90 if ((di.base1 + di.size1) <= BL32_BASE) {
91 NOTICE("OP-TEE has been loaded by SCP firmware\n");
92 /* Populate entry point information for BL32 */
93 SET_PARAM_HEAD(&bl32_image_ep_info,
94 PARAM_EP,
95 VERSION_1,
96 0);
97 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
98 bl32_image_ep_info.pc = BL32_BASE;
99 bl32_image_ep_info.spsr = sq_get_spsr_for_bl32_entry();
100 } else {
101 NOTICE("OP-TEE has not been loaded by SCP firmware\n");
102 }
103 #endif /* SPD_opteed */
104
105 /* Populate entry point information for BL33 */
106 SET_PARAM_HEAD(&bl33_image_ep_info,
107 PARAM_EP,
108 VERSION_1,
109 0);
110 /*
111 * Tell BL31 where the non-trusted software image
112 * is located and the entry state information
113 */
114 bl33_image_ep_info.pc = PRELOADED_BL33_BASE;
115 bl33_image_ep_info.spsr = sq_get_spsr_for_bl33_entry();
116 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
117 }
118
sq_configure_sys_timer(void)119 static void sq_configure_sys_timer(void)
120 {
121 unsigned int reg_val;
122
123 reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT);
124 reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT);
125 reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT);
126 mmio_write_32(SQ_SYS_TIMCTL_BASE +
127 CNTACR_BASE(PLAT_SQ_NSTIMER_FRAME_ID), reg_val);
128
129 reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_SQ_NSTIMER_FRAME_ID));
130 mmio_write_32(SQ_SYS_TIMCTL_BASE + CNTNSAR, reg_val);
131 }
132
bl31_platform_setup(void)133 void bl31_platform_setup(void)
134 {
135 /* Initialize the CCN interconnect */
136 plat_sq_interconnect_init();
137 plat_sq_interconnect_enter_coherency();
138
139 /* Initialize the GIC driver, cpu and distributor interfaces */
140 sq_gic_driver_init();
141 sq_gic_init();
142
143 /* Enable and initialize the System level generic timer */
144 mmio_write_32(SQ_SYS_CNTCTL_BASE + CNTCR_OFF,
145 CNTCR_FCREQ(0U) | CNTCR_EN);
146
147 /* Allow access to the System counter timer module */
148 sq_configure_sys_timer();
149 }
150
bl31_plat_runtime_setup(void)151 void bl31_plat_runtime_setup(void)
152 {
153 struct draminfo *di = (struct draminfo *)(unsigned long)DRAMINFO_BASE;
154
155 sq_scp_get_draminfo(di);
156 }
157
bl31_plat_arch_setup(void)158 void bl31_plat_arch_setup(void)
159 {
160 static const mmap_region_t secure_partition_mmap[] = {
161 #if SPM_MM
162 MAP_REGION_FLAT(PLAT_SPM_BUF_BASE,
163 PLAT_SPM_BUF_SIZE,
164 MT_RW_DATA | MT_SECURE),
165 MAP_REGION_FLAT(PLAT_SQ_SP_PRIV_BASE,
166 PLAT_SQ_SP_PRIV_SIZE,
167 MT_RW_DATA | MT_SECURE),
168 #endif
169 {0},
170 };
171
172 sq_mmap_setup(BL31_BASE, BL31_SIZE, secure_partition_mmap);
173 enable_mmu_el3(XLAT_TABLE_NC);
174
175 #if SPM_MM
176 memcpy((void *)SPM_SHIM_EXCEPTIONS_START,
177 (void *)SPM_SHIM_EXCEPTIONS_LMA,
178 (uintptr_t)SPM_SHIM_EXCEPTIONS_END -
179 (uintptr_t)SPM_SHIM_EXCEPTIONS_START);
180 #endif
181 }
182
bl31_plat_enable_mmu(uint32_t flags)183 void bl31_plat_enable_mmu(uint32_t flags)
184 {
185 enable_mmu_el3(flags | XLAT_TABLE_NC);
186 }
187
plat_get_syscnt_freq2(void)188 unsigned int plat_get_syscnt_freq2(void)
189 {
190 unsigned int counter_base_frequency;
191
192 /* Read the frequency from Frequency modes table */
193 counter_base_frequency = mmio_read_32(SQ_SYS_CNTCTL_BASE + CNTFID_OFF);
194
195 /* The first entry of the frequency modes table must not be 0 */
196 if (counter_base_frequency == 0)
197 panic();
198
199 return counter_base_frequency;
200 }
201