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Searched refs:MRM0r (Results 1 – 25 of 37) sorted by relevance

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/external/llvm/utils/TableGen/
DX86RecognizableInstr.cpp108 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, enumerator
151 (form >= X86Local::MRM0r && form <= X86Local::MRM7r)); in isRegFormat()
715 case X86Local::MRM0r: in emitInstructionSpecifier()
852 case X86Local::MRM0r: case X86Local::MRM1r: in emitDecodePath()
856 filter = new ExtendedFilter(true, Form - X86Local::MRM0r); in emitDecodePath()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrShiftRotate.td459 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
462 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
465 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
468 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
473 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
476 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
480 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
484 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
490 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
493 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
DX86InstrFPStack.td323 def ADD_FST0r : FPST0rInst <MRM0r, "fadd\t{$op, %st|st, $op}">;
324 def ADD_FrST0 : FPrST0Inst <MRM0r, "fadd\t{%st, $op|$op, st}">;
325 def ADD_FPrST0 : FPrST0PInst<MRM0r, "faddp\t{%st, $op|$op, st}">;
453 def CMOVB_F : FPI<0xDA, MRM0r, (outs), (ins RSTi:$op),
461 def CMOVNB_F : FPI<0xDB, MRM0r, (outs), (ins RSTi:$op),
601 def LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RSTi:$op), "fld\t$op">;
717 def FFREE : FPI<0xDD, MRM0r, (outs), (ins RSTi:$reg), "ffree\t$reg">;
718 def FFREEP : FPI<0xDF, MRM0r, (outs), (ins RSTi:$reg), "ffreep\t$reg">;
DX86InstrSystem.td372 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
377 def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
382 def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
602 def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
605 def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
DX86InstrArithmetic.td442 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
445 def INC16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
449 def INC32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
453 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "inc{q}\t$dst",
1178 defm ADD : ArithBinOp_RF<0x00, 0x02, 0x04, "add", MRM0r, MRM0m,
1247 def TEST8ri : BinOpRI_F<0xF6, "test", Xi8 , X86testpat, MRM0r>;
1248 def TEST16ri : BinOpRI_F<0xF6, "test", Xi16, X86testpat, MRM0r>;
1249 def TEST32ri : BinOpRI_F<0xF6, "test", Xi32, X86testpat, MRM0r>;
1251 def TEST64ri32 : BinOpRI_F<0xF6, "test", Xi64, X86testpat, MRM0r>;
DX86InstrInfo.td1257 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
1259 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>,
1351 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>,
1554 def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
1566 def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src),
1569 def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src),
1572 def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src),
2685 def LLWPCB : I<0x12, MRM0r, (outs), (ins GR32:$src), "llwpcb\t$src",
2690 def LLWPCB64 : I<0x12, MRM0r, (outs), (ins GR64:$src), "llwpcb\t$src",
2696 def rri : Ii32<0x12, MRM0r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl),
/external/llvm/lib/Target/X86/
DX86InstrShiftRotate.td471 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
474 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
477 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
480 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
485 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
488 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
492 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
496 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
503 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
507 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
DX86InstrFPStack.td268 def ADD_FST0r : FPST0rInst <MRM0r, "fadd\t$op">;
269 def ADD_FrST0 : FPrST0Inst <MRM0r, "fadd\t{%st(0), $op|$op, st(0)}">;
270 def ADD_FPrST0 : FPrST0PInst<MRM0r, "faddp\t$op">;
383 def CMOVB_F : FPI<0xDA, MRM0r, (outs), (ins RST:$op),
391 def CMOVNB_F : FPI<0xDB, MRM0r, (outs), (ins RST:$op),
539 def LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RST:$op), "fld\t$op", IIC_FLD>;
632 def FFREE : FPI<0xDD, MRM0r, (outs), (ins RST:$reg),
DX86InstrSystem.td404 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
408 def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
413 def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
573 def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
576 def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
DX86InstrArithmetic.td455 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
460 def INC16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
464 def INC32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
468 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "inc{q}\t$dst",
1197 defm ADD : ArithBinOp_RF<0x00, 0x02, 0x04, "add", MRM0r, MRM0m,
1237 def TEST8ri : BinOpRI_F<0xF6, "test", Xi8 , X86testpat, MRM0r>;
1238 def TEST16ri : BinOpRI_F<0xF6, "test", Xi16, X86testpat, MRM0r>;
1239 def TEST32ri : BinOpRI_F<0xF6, "test", Xi32, X86testpat, MRM0r>;
1240 def TEST64ri32 : BinOpRI_F<0xF6, "test", Xi64, X86testpat, MRM0r>;
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h295 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 enumerator
685 case X86II::MRM0r: case X86II::MRM1r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp869 case X86II::MRM0r: case X86II::MRM1r: in EmitVEXOpcodePrefix()
1020 case X86II::MRM0r: case X86II::MRM1r: in DetermineREXPrefix()
1355 case X86II::MRM0r: case X86II::MRM1r: in encodeInstruction()
1365 (Form == X86II::MRMXr) ? 0 : Form-X86II::MRM0r, in encodeInstruction()
/external/llvm-project/llvm/lib/Target/X86/
DX86InstrShiftRotate.td459 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
462 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
465 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
468 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
473 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
476 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
480 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
484 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
490 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
493 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
DX86InstrFPStack.td317 def ADD_FST0r : FPST0rInst <MRM0r, "fadd\t{$op, %st|st, $op}">;
318 def ADD_FrST0 : FPrST0Inst <MRM0r, "fadd\t{%st, $op|$op, st}">;
319 def ADD_FPrST0 : FPrST0PInst<MRM0r, "faddp\t{%st, $op|$op, st}">;
449 def CMOVB_F : FPI<0xDA, MRM0r, (outs), (ins RSTi:$op),
457 def CMOVNB_F : FPI<0xDB, MRM0r, (outs), (ins RSTi:$op),
603 def LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RSTi:$op), "fld\t$op">;
713 def FFREE : FPI<0xDD, MRM0r, (outs), (ins RSTi:$reg), "ffree\t$reg">;
714 def FFREEP : FPI<0xDF, MRM0r, (outs), (ins RSTi:$reg), "ffreep\t$reg">;
DX86InstrSystem.td382 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
387 def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
392 def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
612 def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
615 def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
DX86InstrArithmetic.td442 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
445 def INC16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
449 def INC32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
453 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "inc{q}\t$dst",
1178 defm ADD : ArithBinOp_RF<0x00, 0x02, 0x04, "add", MRM0r, MRM0m,
1396 def TEST8ri : BinOpRI_F<0xF6, "test", Xi8 , X86testpat, MRM0r>;
1397 def TEST16ri : BinOpRI_F<0xF6, "test", Xi16, X86testpat, MRM0r>;
1398 def TEST32ri : BinOpRI_F<0xF6, "test", Xi32, X86testpat, MRM0r>;
1399 def TEST64ri32 : BinOpRI_F<0xF6, "test", Xi64, X86testpat, MRM0r>;
/external/llvm-project/llvm/utils/TableGen/
DX86RecognizableInstr.h123 MRM0r = 48, MRM1r = 49, MRM2r = 50, MRM3r = 51, enumerator
DX86RecognizableInstr.cpp654 case X86Local::MRM0r: in emitInstructionSpecifier()
794 case X86Local::MRM0r: case X86Local::MRM1r: in emitDecodePath()
798 filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0r); in emitDecodePath()
DX86FoldTablesEmitter.cpp429 if ((MemFormNum == X86Local::MRM0m && RegFormNum == X86Local::MRM0r) || in areOppositeForms()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h666 MRM0r = 56, MRM1r = 57, MRM2r = 58, MRM3r = 59, // Format /0 /1 /2 /3 enumerator
1055 case X86II::MRM0r: case X86II::MRM1r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp1084 case X86II::MRM0r: in emitVEXOpcodePrefix()
1239 case X86II::MRM0r: in determineREXPrefix()
1628 case X86II::MRM0r: in encodeInstruction()
1642 (Form == X86II::MRMXr) ? 0 : Form - X86II::MRM0r, CurByte, in encodeInstruction()
/external/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h717 MRM0r = 48, MRM1r = 49, MRM2r = 50, MRM3r = 51, // Format /0 /1 /2 /3 enumerator
1128 case X86II::MRM0r: case X86II::MRM1r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp1116 case X86II::MRM0r: in emitVEXOpcodePrefix()
1276 case X86II::MRM0r: in emitREXPrefix()
1649 case X86II::MRM0r: in encodeInstruction()
1663 (Form == X86II::MRMXr) ? 0 : Form - X86II::MRM0r, OS); in encodeInstruction()
/external/llvm-project/llvm/test/TableGen/
DTargetInstrInfo.td52 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
/external/llvm/test/TableGen/
DTargetInstrInfo.td52 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;

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