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Searched refs:MRMSrcReg4VOp3 (Results 1 – 17 of 17) sorted by relevance

/external/llvm-project/llvm/lib/Target/X86/
DX86InstrAMX.td61 def TDPBSSD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
65 def TDPBSUD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
69 def TDPBUSD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
73 def TDPBUUD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
105 def TDPBF16PS : I<0x5c, MRMSrcReg4VOp3, (outs TILE:$dst),
DX86InstrXOP.td96 def rr : IXOP<opc, MRMSrcReg4VOp3, (outs VR128:$dst),
DX86InstrFormats.td46 def MRMSrcReg4VOp3 : Format<42>;
DX86InstrShiftRotate.td888 def rr : I<0xF7, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2),
DX86InstrInfo.td2562 def rr : I<opc, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2588 def rr : I<opc, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2),
/external/llvm-project/llvm/utils/TableGen/
DX86RecognizableInstr.h119 MRMSrcReg4VOp3 = 42, enumerator
DX86RecognizableInstr.cpp572 case X86Local::MRMSrcReg4VOp3: in emitInstructionSpecifier()
776 case X86Local::MRMSrcReg4VOp3: in emitDecodePath()
DX86FoldTablesEmitter.cpp444 RegFormNum == X86Local::MRMSrcReg4VOp3) || in areOppositeForms()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h642 MRMSrcReg4VOp3 = 50, enumerator
1050 case X86II::MRMSrcReg4VOp3: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp1031 case X86II::MRMSrcReg4VOp3: { in emitVEXOpcodePrefix()
1523 case X86II::MRMSrcReg4VOp3: { in encodeInstruction()
/external/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h693 MRMSrcReg4VOp3 = 42, enumerator
1122 case X86II::MRMSrcReg4VOp3: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp1054 case X86II::MRMSrcReg4VOp3: { in emitVEXOpcodePrefix()
1542 case X86II::MRMSrcReg4VOp3: { in encodeInstruction()
/external/llvm-project/llvm/tools/llvm-exegesis/lib/X86/
DTarget.cpp68 case X86II::MRMSrcReg4VOp3: in isInvalidMemoryInstr()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrXOP.td96 def rr : IXOP<opc, MRMSrcReg4VOp3, (outs VR128:$dst),
DX86InstrFormats.td42 def MRMSrcReg4VOp3 : Format<50>;
DX86InstrShiftRotate.td888 def rr : I<0xF7, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2),
DX86InstrInfo.td2496 def rr : I<opc, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2522 def rr : I<opc, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2),