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Searched refs:MUL2 (Results 1 – 25 of 52) sorted by relevance

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/external/llvm-project/llvm/test/Transforms/Reassociate/
Dwrap-flags.ll12 ; CHECK-NEXT: [[MUL2:%.*]] = add i32 [[MUL]], 1
13 ; CHECK-NEXT: ret i32 [[MUL2]]
26 ; CHECK-NEXT: [[MUL2:%.*]] = add i32 [[MUL]], 1
27 ; CHECK-NEXT: ret i32 [[MUL2]]
40 ; CHECK-NEXT: [[MUL2:%.*]] = add i32 [[MUL]], 1
41 ; CHECK-NEXT: ret i32 [[MUL2]]
54 ; CHECK-NEXT: [[MUL2:%.*]] = add i32 [[MUL]], 1
55 ; CHECK-NEXT: ret i32 [[MUL2]]
68 ; CHECK-NEXT: [[MUL2:%.*]] = add i32 [[MUL]], 1
69 ; CHECK-NEXT: ret i32 [[MUL2]]
Dcanonicalize-neg-const.ll205 ; CHECK-NEXT: [[MUL2:%.*]] = fmul double [[MUL1]], 4.000000e+00
206 ; CHECK-NEXT: [[ADD:%.*]] = fadd double [[A]], [[MUL2]]
220 ; CHECK-NEXT: [[MUL2:%.*]] = fmul double [[MUL1]], 4.000000e+00
221 ; CHECK-NEXT: [[MUL3:%.*]] = fmul double [[MUL2]], 5.000000e+00
250 ; CHECK-NEXT: [[MUL2:%.*]] = fmul double [[MUL1]], 4.000000e+00
251 ; CHECK-NEXT: [[TMP1:%.*]] = fadd double [[A]], [[MUL2]]
265 ; CHECK-NEXT: [[MUL2:%.*]] = fmul double [[MUL1]], 4.000000e+00
266 ; CHECK-NEXT: [[MUL3:%.*]] = fmul double [[MUL2]], 5.000000e+00
400 ; CHECK-NEXT: [[MUL2:%.*]] = fmul double [[DIV1]], 4.000000e+00
401 ; CHECK-NEXT: [[DIV3:%.*]] = fdiv double [[MUL2]], 5.000000e+00
[all …]
Dmixed-fast-nonfast-fp.ll26 ; CHECK-NEXT: [[MUL2:%.*]] = fmul fast float [[B:%.*]], [[A]]
30 ; CHECK-NEXT: [[ADD2:%.*]] = fadd reassoc float [[MUL2]], [[MUL4]]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dfmul-2-combine-multi-use.ll44 ; GCN-DAG: v_add_f32_e64 [[MUL2:v[0-9]+]], [[X:s[0-9]+]], s{{[0-9]+}}
47 ; GCN-DAG: buffer_store_dword [[MUL2]]
60 ; GCN-DAG: v_add_f32_e64 [[MUL2:v[0-9]+]], |[[X:s[0-9]+]]|, |s{{[0-9]+}}|
63 ; GCN-DAG: buffer_store_dword [[MUL2]]
150 ; GCN-DAG: v_add_f16_e64 [[MUL2:v[0-9]+]], [[X:s[0-9]+]], s{{[0-9]+}}
154 ; GFX10-FLUSH-DAG: v_add_f16_e32 [[MAD:v[0-9]+]], s{{[0-9]+}}, [[MUL2]]
157 ; GCN-DAG: buffer_store_short [[MUL2]]
172 ; GCN-DAG: v_add_f16_e64 [[MUL2:v[0-9]+]], |[[X:s[0-9]+]]|, |s{{[0-9]+}}|
176 ; GFX10-FLUSH-DAG: v_add_f16_e32 [[MAD:v[0-9]+]], s{{[0-9]+}}, [[MUL2]]
179 ; GCN-DAG: buffer_store_short [[MUL2]]
[all …]
Dfexp.ll127 ; VI-NEXT: v_mul_f16_e32 [[MUL2:v[0-9]+]], [[SREG]], v{{[0-9]+}}
129 ; VI-NEXT: v_exp_f16_e32 [[MUL2]], [[MUL2]]
130 ; VI-NEXT: v_or_b32_e32 v{{[0-9]+}}, [[MUL2]], [[MUL1]]
181 ; VI-NEXT: v_mul_f16_e32 [[MUL2:v[0-9]+]], [[SREG]], v0
186 ; VI-NEXT: v_exp_f16_e32 [[EXP3:v[0-9]+]], [[MUL2]]
197 ; GFX9-NEXT: v_mul_f16_e32 [[MUL2:v[0-9]+]], [[SREG]], v0
201 ; GFX9-NEXT: v_exp_f16_e32 [[EXP2:v[0-9]+]], [[MUL2]]
Dfmuladd.f16.ll84 ; GFX10-FLUSH: v_add_f16_e32 [[MUL2:v[0-9]+]], [[R1]], [[R1]]
85 ; GFX10-FLUSH: v_add_f16_e32 [[RESULT:v[0-9]+]], [[MUL2]], [[R2]]
114 ; GFX10-FLUSH: v_add_f16_e32 [[MUL2:v[0-9]+]], [[R1]], [[R1]]
115 ; GFX10-FLUSH: v_add_f16_e32 [[RESULT:v[0-9]+]], [[MUL2]], [[R2]]
149 ; GFX10-FLUSH: v_add_f16_e32 [[MUL2:v[0-9]+]], [[R1]], [[R1]]
150 ; GFX10-FLUSH: v_add_f16_e32 [[RESULT:v[0-9]+]], [[MUL2]], [[R2]]
186 ; GFX10-FLUSH: v_add_f16_e32 [[MUL2:v[0-9]+]], [[R1]], [[R1]]
187 ; GFX10-FLUSH: v_add_f16_e32 [[RESULT:v[0-9]+]], [[R2]], [[MUL2]]
217 ; GFX10-FLUSH: v_add_f16_e32 [[MUL2:v[0-9]+]], [[R1]], [[R1]]
218 ; GFX10-FLUSH: v_sub_f16_e32 [[RESULT:v[0-9]+]], [[R2]], [[MUL2]]
[all …]
/external/llvm-project/polly/test/Isl/CodeGen/MemAccess/
Dcodegen_simple_md.ll60 ; WITHCONST: %[[MUL2:[._a-zA-Z0-9]+]] = mul nsw i64 2, %[[IVIn]]
61 ; WITHCONST: %[[SUM1:[._a-zA-Z0-9]+]] = add nsw i64 %[[MUL1]], %[[MUL2]]
69 ; WITHOUTCONST: %[[MUL2:[._a-zA-Z0-9]+]] = mul nsw i64 2, %[[IVIn]]
70 ; WITHOUTCONST: %[[SUM1:[._a-zA-Z0-9]+]] = add nsw i64 %[[MUL1]], %[[MUL2]]
Dcodegen_simple_md_float.ll57 ; WITHCONST: %[[MUL2:[._a-zA-Z0-9]+]] = mul nsw i64 2, %[[IVIn]]
58 ; WITHCONST: %[[SUM1:[._a-zA-Z0-9]+]] = add nsw i64 %[[MUL1]], %[[MUL2]]
66 ; WITHOUTCONST: %[[MUL2:[._a-zA-Z0-9]+]] = mul nsw i64 2, %[[IVIn]]
67 ; WITHOUTCONST: %[[SUM1:[._a-zA-Z0-9]+]] = add nsw i64 %[[MUL1]], %[[MUL2]]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dlegalize-mul.mir85 ; GFX6: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV3]]
87 ; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]]
98 ; GFX8: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV3]]
100 ; GFX8: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]]
111 ; GFX9: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[UV]], [[UV3]]
113 ; GFX9: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]]
138 ; GFX6: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[UV4]], [[UV7]]
140 ; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]]
163 ; GFX8: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[UV4]], [[UV7]]
165 ; GFX8: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]]
[all …]
Dlegalize-umulh.mir76 ; GFX8: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV3]]
79 ; GFX8: [[UADDO4:%[0-9]+]]:_(s32), [[UADDO5:%[0-9]+]]:_(s1) = G_UADDO [[MUL2]], [[UMULH1]]
104 ; GFX9: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[UV1]], [[UV3]]
107 ; GFX9: [[UADDO4:%[0-9]+]]:_(s32), [[UADDO5:%[0-9]+]]:_(s1) = G_UADDO [[MUL2]], [[UMULH1]]
321 ; GFX8: [[MUL2:%[0-9]+]]:_(s16) = G_MUL [[AND4]], [[AND5]]
322 ; GFX8: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[MUL2]], [[C1]](s16)
572 ; GFX8: [[MUL2:%[0-9]+]]:_(s16) = G_MUL [[AND4]], [[AND5]]
573 ; GFX8: [[LSHR8:%[0-9]+]]:_(s16) = G_LSHR [[MUL2]], [[C4]](s16)
Dlegalize-udiv.mir135 ; GFX6: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[SUB3]], [[FPTOUI1]]
136 ; GFX6: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[MUL2]]
184 ; GFX8: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[SUB3]], [[FPTOUI1]]
185 ; GFX8: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[MUL2]]
233 ; GFX9: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[SUB3]], [[FPTOUI1]]
234 ; GFX9: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[MUL2]]
288 ; GFX6: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[FPTOUI1]]
290 ; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]]
441 ; GFX8: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[FPTOUI1]]
443 ; GFX8: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]]
[all …]
Dlegalize-urem.mir123 ; GFX6: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[SUB4]], [[FPTOUI1]]
124 ; GFX6: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[MUL2]]
167 ; GFX8: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[SUB4]], [[FPTOUI1]]
168 ; GFX8: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[MUL2]]
211 ; GFX9: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[SUB4]], [[FPTOUI1]]
212 ; GFX9: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[MUL2]]
264 ; GFX6: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[FPTOUI1]]
266 ; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]]
410 ; GFX8: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[FPTOUI1]]
412 ; GFX8: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]]
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dfmul-2-combine-multi-use.ll30 ; GCN-DAG: v_add_f32_e64 [[MUL2:v[0-9]+]], [[X:s[0-9]+]], s{{[0-9]+}}
32 ; GCN-DAG: buffer_store_dword [[MUL2]]
45 ; GCN-DAG: v_add_f32_e64 [[MUL2:v[0-9]+]], |[[X:s[0-9]+]]|, |s{{[0-9]+}}|
47 ; GCN-DAG: buffer_store_dword [[MUL2]]
/external/llvm-project/llvm/test/Transforms/SLPVectorizer/X86/
DPR36280.ll11 ; CHECK-NEXT: [[MUL2:%.*]] = fmul float [[P2]], [[Y:%.*]]
13 ; CHECK-NEXT: [[ADD2:%.*]] = fadd float [[MUL2]], [[ADD1]]
Dcrash_binaryop.ll20 ; CHECK-NEXT: [[MUL2:%.*]] = fmul double [[ADD2]], 0.000000e+00
21 ; CHECK-NEXT: [[BINARYOP_B:%.*]] = fadd double [[POSTADD1_PHI]], [[MUL2]]
/external/tensorflow/tensorflow/compiler/mlir/tensorflow/tests/
Dsink_constant.mlir26 // CHECK-NEXT: %[[MUL2:.*]] = "tf.Mul"(%[[MUL1]], %[[CST2]])
27 // CHECK-NEXT: %[[MUL3:.*]] = "tf.Mul"(%[[MUL2]], %[[CST3]])
/external/webp/src/dsp/
Ddec.c41 #define MUL2(a) (((a) * 35468) >> 16) macro
51 const int c = MUL2(in[4]) - MUL1(in[12]); // [-3783, 3783] in TransformOne_C()
52 const int d = MUL1(in[4]) + MUL2(in[12]); // [-3785, 3781] in TransformOne_C()
72 const int c = MUL2(tmp[4]) - MUL1(tmp[12]); in TransformOne_C()
73 const int d = MUL1(tmp[4]) + MUL2(tmp[12]); in TransformOne_C()
86 const int c4 = MUL2(in[4]); in TransformAC3_C()
88 const int c1 = MUL2(in[1]); in TransformAC3_C()
96 #undef MUL2
/external/libvpx/libvpx/vp9/encoder/mips/msa/
Dvp9_fdct_msa.h93 MUL2(in0_r_m, constant_m, in3_r_m, constant_m, s1_m, s0_m); \
106 MUL2(in2_r_m, constant_m, s2_m, constant_m, s3_m, in1_r_m); \
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
Dmul.mir234 ; MIPS32: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY1]]
236 ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]]
283 ; MIPS32: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[LOAD]], [[COPY1]]
285 ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]]
286 ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[MUL2]]
393 ; MIPS32: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[COPY3]], [[COPY1]]
396 ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[MUL2]], [[UMULH1]]
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dfmul.ll352 ; CHECK-NEXT: [[MUL2:%.*]] = fmul float [[MUL]], [[SUB1]]
353 ; CHECK-NEXT: ret float [[MUL2]]
365 ; CHECK-NEXT: [[MUL2:%.*]] = fmul float [[MUL]], [[SUB1]]
366 ; CHECK-NEXT: ret float [[MUL2]]
452 ; CHECK-NEXT: [[MUL2:%.*]] = fmul double [[SQRT]], [[F]]
453 ; CHECK-NEXT: ret double [[MUL2]]
551 ; CHECK-NEXT: [[MUL2:%.*]] = fmul reassoc float [[TMP1]], [[Y:%.*]]
552 ; CHECK-NEXT: ret float [[MUL2]]
564 ; CHECK-NEXT: [[MUL2:%.*]] = fmul fast float [[TMP1]], [[Y:%.*]]
565 ; CHECK-NEXT: ret float [[MUL2]]
[all …]
Dreassociate-nuw.ll71 ; CHECK-NEXT: [[MUL2:%.*]] = mul nuw i32 [[MUL1]], 45
72 ; CHECK-NEXT: ret i32 [[MUL2]]
Dmul.ll674 ; CHECK-NEXT: [[MUL2:%.*]] = mul i32 [[MUL]], [[NEG]]
675 ; CHECK-NEXT: ret i32 [[MUL2]]
1034 ; CHECK-NEXT: [[MUL2:%.*]] = shl i32 [[MUL1_NEG]], 2
1035 ; CHECK-NEXT: ret i32 [[MUL2]]
1047 ; CHECK-NEXT: [[MUL2:%.*]] = mul i32 [[MUL1]], -4
1048 ; CHECK-NEXT: ret i32 [[MUL2]]
1061 ; CHECK-NEXT: [[MUL2:%.*]] = mul i32 [[MUL1]], -4
1062 ; CHECK-NEXT: ret i32 [[MUL2]]
1076 ; CHECK-NEXT: [[MUL2:%.*]] = mul i32 [[MUL1]], -4
1077 ; CHECK-NEXT: ret i32 [[MUL2]]
/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
Dlegalizer-combiner.mir109 ; CHECK: [[MUL2:%[0-9]+]]:_(s64) = G_MUL [[LOAD]], [[UV1]]
111 ; CHECK: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[MUL1]], [[MUL2]]
/external/llvm-project/llvm/test/Transforms/SimplifyCFG/PowerPC/
Dprefer-fma.ll34 ; CHECK-NEXT: [[MUL2:%.*]] = fsub fast double [[TMP6]], [[TMP7]]
35 ; CHECK-NEXT: store double [[MUL2]], double* [[Y]], align 8
/external/llvm/lib/Target/AMDGPU/
DSIDefines.h101 MUL2 = 1, enumerator

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