| /external/llvm/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 69 unsigned MulOpc, unsigned AddSubOpc,
273 unsigned MulOpc, unsigned AddSubOpc, in ExpandFPMLxInstruction() argument
287 const MCInstrDesc &MCID1 = TII->get(MulOpc); in ExpandFPMLxInstruction()
360 unsigned MulOpc, AddSubOpc; in ExpandFPMLxInstructions() local
363 MulOpc, AddSubOpc, NegAcc, HasLane) || in ExpandFPMLxInstructions()
367 ExpandFPMLxInstruction(MBB, MI, MulOpc, AddSubOpc, NegAcc, HasLane); in ExpandFPMLxInstructions()
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| D | ARMBaseInstrInfo.h | 382 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
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| D | ARMBaseInstrInfo.cpp | 57 uint16_t MulOpc; // Expanded multiplication opcode member
93 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc); in ARMBaseInstrInfo()
4149 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, in isFpMLxInstruction() argument
4157 MulOpc = Entry.MulOpc; in isFpMLxInstruction()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 68 unsigned MulOpc, unsigned AddSubOpc,
270 unsigned MulOpc, unsigned AddSubOpc, in ExpandFPMLxInstruction() argument
284 const MCInstrDesc &MCID1 = TII->get(MulOpc); in ExpandFPMLxInstruction()
354 unsigned MulOpc, AddSubOpc; in ExpandFPMLxInstructions() local
357 MulOpc, AddSubOpc, NegAcc, HasLane) || in ExpandFPMLxInstructions()
361 ExpandFPMLxInstruction(MBB, MI, MulOpc, AddSubOpc, NegAcc, HasLane); in ExpandFPMLxInstructions()
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| D | ARMBaseInstrInfo.h | 430 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
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| D | ARMBaseInstrInfo.cpp | 80 uint16_t MulOpc; // Expanded multiplication opcode member
116 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc); in ARMBaseInstrInfo()
4797 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, in isFpMLxInstruction() argument
4805 MulOpc = Entry.MulOpc; in isFpMLxInstruction()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 68 unsigned MulOpc, unsigned AddSubOpc,
270 unsigned MulOpc, unsigned AddSubOpc, in ExpandFPMLxInstruction() argument
284 const MCInstrDesc &MCID1 = TII->get(MulOpc); in ExpandFPMLxInstruction()
354 unsigned MulOpc, AddSubOpc; in ExpandFPMLxInstructions() local
357 MulOpc, AddSubOpc, NegAcc, HasLane) || in ExpandFPMLxInstructions()
361 ExpandFPMLxInstruction(MBB, MI, MulOpc, AddSubOpc, NegAcc, HasLane); in ExpandFPMLxInstructions()
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| D | ARMBaseInstrInfo.h | 485 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
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| D | ARMBaseInstrInfo.cpp | 84 uint16_t MulOpc; // Expanded multiplication opcode member
120 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc); in ARMBaseInstrInfo()
4833 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, in isFpMLxInstruction() argument
4841 MulOpc = Entry.MulOpc; in isFpMLxInstruction()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 2880 unsigned MulOpc, unsigned ZeroReg) { in canCombineWithMUL() argument
2881 return canCombine(MBB, MO, MulOpc, ZeroReg, true); in canCombineWithMUL()
2887 unsigned MulOpc) { in canCombineWithFMUL() argument
2888 return canCombine(MBB, MO, MulOpc); in canCombineWithFMUL()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 3698 unsigned MulOpc, unsigned ZeroReg) { in canCombineWithMUL() argument
3699 return canCombine(MBB, MO, MulOpc, ZeroReg, true); in canCombineWithMUL()
3705 unsigned MulOpc) { in canCombineWithFMUL() argument
3706 return canCombine(MBB, MO, MulOpc); in canCombineWithFMUL()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 3289 unsigned MulOpc = Signed ? AMDGPUISD::MUL_I24 : AMDGPUISD::MUL_U24; in getMul24() local
3290 return DAG.getNode(MulOpc, SL, MVT::i32, N0, N1); in getMul24()
3297 unsigned MulOpc = Signed ? AMDGPUISD::MUL_LOHI_I24 : AMDGPUISD::MUL_LOHI_U24; in getMul24() local
3299 SDValue Mul = DAG.getNode(MulOpc, SL, in getMul24()
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 4074 unsigned MulOpc, unsigned ZeroReg) { in canCombineWithMUL() argument
4075 return canCombine(MBB, MO, MulOpc, ZeroReg, true); in canCombineWithMUL()
4081 unsigned MulOpc) { in canCombineWithFMUL() argument
4082 return canCombine(MBB, MO, MulOpc); in canCombineWithFMUL()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 3295 unsigned MulOpc = Signed ? AMDGPUISD::MUL_I24 : AMDGPUISD::MUL_U24; in getMul24() local
3296 return DAG.getNode(MulOpc, SL, MVT::i32, N0, N1); in getMul24()
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