/external/vixl/test/test-trace-reference/ |
D | log-cpufeatures-custom | 322 0x~~~~~~~~~~~~~~~~ 7ef3d44d fabd d13, d2, d19 ### {FP, NEON} ### 323 0x~~~~~~~~~~~~~~~~ 7ebed548 fabd s8, s10, s30 ### {FP, NEON} ### 326 0x~~~~~~~~~~~~~~~~ 7e70eee1 facge d1, d23, d16 ### {FP, NEON} ### 327 0x~~~~~~~~~~~~~~~~ 7e21ee24 facge s4, s17, s1 ### {FP, NEON} ### 328 0x~~~~~~~~~~~~~~~~ 7ef8eea2 facgt d2, d21, d24 ### {FP, NEON} ### 329 0x~~~~~~~~~~~~~~~~ 7eacef4c facgt s12, s26, s12 ### {FP, NEON} ### 336 0x~~~~~~~~~~~~~~~~ 5e6ae513 fcmeq d19, d8, d10 ### {FP, NEON} ### 337 0x~~~~~~~~~~~~~~~~ 5ee0da40 fcmeq d0, d18, #0.0 ### {FP, NEON} ### 338 0x~~~~~~~~~~~~~~~~ 5e3ee481 fcmeq s1, s4, s30 ### {FP, NEON} ### 339 0x~~~~~~~~~~~~~~~~ 5ea0dbb6 fcmeq s22, s29, #0.0 ### {FP, NEON} ### [all …]
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D | log-cpufeatures | 322 0x~~~~~~~~~~~~~~~~ 7ef3d44d fabd d13, d2, d19 // Needs: FP, NEON 323 0x~~~~~~~~~~~~~~~~ 7ebed548 fabd s8, s10, s30 // Needs: FP, NEON 326 0x~~~~~~~~~~~~~~~~ 7e70eee1 facge d1, d23, d16 // Needs: FP, NEON 327 0x~~~~~~~~~~~~~~~~ 7e21ee24 facge s4, s17, s1 // Needs: FP, NEON 328 0x~~~~~~~~~~~~~~~~ 7ef8eea2 facgt d2, d21, d24 // Needs: FP, NEON 329 0x~~~~~~~~~~~~~~~~ 7eacef4c facgt s12, s26, s12 // Needs: FP, NEON 336 0x~~~~~~~~~~~~~~~~ 5e6ae513 fcmeq d19, d8, d10 // Needs: FP, NEON 337 0x~~~~~~~~~~~~~~~~ 5ee0da40 fcmeq d0, d18, #0.0 // Needs: FP, NEON 338 0x~~~~~~~~~~~~~~~~ 5e3ee481 fcmeq s1, s4, s30 // Needs: FP, NEON 339 0x~~~~~~~~~~~~~~~~ 5ea0dbb6 fcmeq s22, s29, #0.0 // Needs: FP, NEON [all …]
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/external/llvm-project/llvm/test/MC/ARM/ |
D | fullfp16-neon-neg.s | 8 @ CHECK: instruction requires: {{full half-float|NEON}} 9 @ CHECK: instruction requires: {{full half-float|NEON}} 13 @ CHECK: instruction requires: {{full half-float|NEON}} 14 @ CHECK: instruction requires: {{full half-float|NEON}} 18 @ CHECK: instruction requires: {{full half-float|NEON}} 19 @ CHECK: instruction requires: {{full half-float|NEON}} 23 @ CHECK: instruction requires: {{full half-float|NEON}} 24 @ CHECK: instruction requires: {{full half-float|NEON}} 28 @ CHECK: instruction requires: {{full half-float|NEON}} 29 @ CHECK: instruction requires: {{full half-float|NEON}} [all …]
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D | neon-mov-vfp.s | 3 …known -show-encoding -mattr=+neon < %s 2>&1 | FileCheck %s --check-prefix=NEON --check-prefix=CHECK 4 …known -show-encoding -mattr=+neon < %s 2>&1 | FileCheck %s --check-prefix=NEON --check-prefix=CHECK 6 @ The 32-bit variants of the NEON scalar move instructions are also available 14 @ VFP-DAG: error: instruction requires: NEON 15 @ VFP-DAG: error: instruction requires: NEON 16 @ NEON-DAG: vmov.8 d22[5], r2 @ encoding: 17 @ NEON-DAG: vmov.16 d3[2], r4 @ encoding: 26 @ VFP-DAG: error: instruction requires: NEON 27 @ VFP-DAG: error: instruction requires: NEON 28 @ NEON-DAG: vmov.s8 r2, d22[5] @ encoding: [all …]
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/external/llvm/test/CodeGen/Thumb2/ |
D | aligned-spill.ll | 2 ; RUN: llc < %s -mcpu=cortex-a8 -align-neon-spills=1 | FileCheck %s --check-prefix=NEON 23 ; NEON: f 24 ; NEON: push {r4, r7, lr} 25 ; NEON: sub.w r4, sp, #64 26 ; NEON: bfc r4, #0, #4 28 ; NEON: mov sp, r4 29 ; NEON: vst1.64 {d8, d9, d10, d11}, [r4:128]! 30 ; NEON: vst1.64 {d12, d13, d14, d15}, [r4:128] 36 ; NEON: sub sp, #16 38 ; NEON: add r[[R4:[0-9]+]], sp, #16 [all …]
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/external/llvm-project/llvm/test/CodeGen/Thumb2/ |
D | aligned-spill.ll | 2 ; RUN: llc < %s -mcpu=cortex-a8 -align-neon-spills=1 | FileCheck %s --check-prefix=NEON 23 ; NEON: f 24 ; NEON: push {r4, r7, lr} 25 ; NEON: sub.w r4, sp, #64 26 ; NEON: bfc r4, #0, #4 28 ; NEON: mov sp, r4 29 ; NEON: vst1.64 {d8, d9, d10, d11}, [r4:128]! 30 ; NEON: vst1.64 {d12, d13, d14, d15}, [r4:128] 36 ; NEON: sub sp, #16 38 ; NEON: add r[[R4:[0-9]+]], sp, #16 [all …]
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/external/llvm-project/llvm/test/Transforms/InterleavedAccess/AArch64/ |
D | interleaved-accesses.ll | 1 ; RUN: opt < %s -interleaved-access -S | FileCheck %s -check-prefix=NEON 8 ; NEON-LABEL: @load_factor2( 9 ; NEON-NEXT: [[TMP1:%.*]] = bitcast <16 x i8>* %ptr to <8 x i8>* 10 ; NEON-NEXT: [[LDN:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2.v8i8.p0v8i8(<8 … 11 ; NEON-NEXT: [[TMP2:%.*]] = extractvalue { <8 x i8>, <8 x i8> } [[LDN]], 1 12 ; NEON-NEXT: [[TMP3:%.*]] = extractvalue { <8 x i8>, <8 x i8> } [[LDN]], 0 13 ; NEON-NEXT: ret void 25 ; NEON-LABEL: @load_factor3( 26 ; NEON-NEXT: [[TMP1:%.*]] = bitcast <12 x i32>* %ptr to <4 x i32>* 27 ; NEON-NEXT: [[LDN:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4… [all …]
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/external/llvm-project/llvm/test/CodeGen/ARM/ |
D | funnel-shift-rot.ll | 3 …UN: llc < %s -mtriple=arm-eabi -mattr=+v6t2 -mattr=+neon | FileCheck %s --check-prefixes=CHECK,NEON 98 ; NEON-LABEL: rotl_i64: 99 ; NEON: @ %bb.0: 100 ; NEON-NEXT: .save {r4, r5, r11, lr} 101 ; NEON-NEXT: push {r4, r5, r11, lr} 102 ; NEON-NEXT: and r12, r2, #63 103 ; NEON-NEXT: rsb r2, r2, #0 104 ; NEON-NEXT: rsb r3, r12, #32 105 ; NEON-NEXT: and r4, r2, #63 106 ; NEON-NEXT: subs lr, r12, #32 [all …]
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D | fp_convert.ll | 11 ; RUN: | FileCheck %s -check-prefix=NEON 14 ; RUN: | FileCheck %s -check-prefix=NEON 22 ; NEON-LABEL: test1: 23 ; NEON: vadd.f32 [[D0:d[0-9]+]] 24 ; NEON: vcvt.s32.f32 d0, [[D0]] 34 ; NEON-LABEL: test2: 35 ; NEON: vadd.f32 [[D0:d[0-9]+]] 36 ; NEON: vcvt.u32.f32 d0, [[D0]] 46 ; NEON-LABEL: test3: 47 ; NEON: vcvt.f32.u32 d [all …]
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D | fnmscs.ll | 8 ; RUN: | FileCheck %s -check-prefix=NEON 30 ; NEON-LABEL: t1: 31 ; NEON: vnmla.f32 54 ; NEON-LABEL: t2: 55 ; NEON: vnmla.f32 78 ; NEON-LABEL: t3: 79 ; NEON: vnmla.f64 102 ; NEON-LABEL: t4: 103 ; NEON: vnmla.f64 126 ; NEON-LABEL: t5: [all …]
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D | fcmp-xo.ll | 3 …m-none-eabi -mattr=+execute-only,+fp-armv8,+neon,+neonfp | FileCheck %s --check-prefixes=CHECK,NEON 54 ; NEON-LABEL: float128: 55 ; NEON: @ %bb.0: 56 ; NEON-NEXT: mov.w r0, #1124073472 57 ; NEON-NEXT: vmov.f32 s2, #5.000000e-01 58 ; NEON-NEXT: vmov d3, r0, r0 59 ; NEON-NEXT: vmov.f32 s4, #-5.000000e-01 60 ; NEON-NEXT: vcmp.f32 s6, s0 61 ; NEON-NEXT: vmrs APSR_nzcv, fpscr 62 ; NEON-NEXT: vselgt.f32 s0, s4, s2 [all …]
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D | fmscs.ll | 2 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s -check-prefix=NEON 10 ; NEON-LABEL: t1: 11 ; NEON: vnmls.f32 26 ; NEON-LABEL: t2: 27 ; NEON: vnmls.f64
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/external/llvm-project/llvm/test/Transforms/CodeGenPrepare/ARM/ |
D | sink-free-instructions.ll | 2 ; RUN: opt -mtriple=armv7-apple-darwin < %s -codegenprepare -S | FileCheck -check-prefix=NEON %s 6 ; NEON-LABEL: @sink_zext( 7 ; NEON-NEXT: entry: 8 ; NEON-NEXT: br i1 [[C:%.*]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] 9 ; NEON: if.then: 10 ; NEON-NEXT: [[ZB_1:%.*]] = zext <8 x i8> [[B:%.*]] to <8 x i16> 11 ; NEON-NEXT: [[TMP0:%.*]] = zext <8 x i8> [[A:%.*]] to <8 x i16> 12 ; NEON-NEXT: [[RES_1:%.*]] = add <8 x i16> [[TMP0]], [[ZB_1]] 13 ; NEON-NEXT: ret <8 x i16> [[RES_1]] 14 ; NEON: if.else: [all …]
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/external/clang/lib/CodeGen/ |
D | CGBuiltin.cpp | 2664 { #NameBase, NEON::BI__builtin_neon_ ## NameBase, 0, 0, 0 } 2667 { #NameBase, NEON:: BI__builtin_neon_ ## NameBase, \ 2671 { #NameBase, NEON:: BI__builtin_neon_ ## NameBase, \ 3281 case NEON::BI__builtin_neon_vcled_s64: in EmitCommonNeonSISDBuiltinExpr() 3282 case NEON::BI__builtin_neon_vcled_u64: in EmitCommonNeonSISDBuiltinExpr() 3283 case NEON::BI__builtin_neon_vcles_f32: in EmitCommonNeonSISDBuiltinExpr() 3284 case NEON::BI__builtin_neon_vcled_f64: in EmitCommonNeonSISDBuiltinExpr() 3285 case NEON::BI__builtin_neon_vcltd_s64: in EmitCommonNeonSISDBuiltinExpr() 3286 case NEON::BI__builtin_neon_vcltd_u64: in EmitCommonNeonSISDBuiltinExpr() 3287 case NEON::BI__builtin_neon_vclts_f32: in EmitCommonNeonSISDBuiltinExpr() [all …]
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/external/llvm/test/CodeGen/ARM/ |
D | arm-interleaved-accesses.ll | 1 …riple=arm-eabi -mattr=+neon -lower-interleaved-accesses=true < %s | FileCheck %s -check-prefix=NEON 4 ; NEON-LABEL: load_factor2: 5 ; NEON: vld2.8 {d16, d17}, [r0] 16 ; NEON-LABEL: load_factor3: 17 ; NEON: vld3.32 {d16, d17, d18}, [r0] 29 ; NEON-LABEL: load_factor4: 30 ; NEON: vld4.32 {d16, d18, d20, d22}, [r0]! 31 ; NEON: vld4.32 {d17, d19, d21, d23}, [r0] 43 ; NEON-LABEL: store_factor2: 44 ; NEON: vst2.8 {d16, d17}, [r0] [all …]
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D | fp_convert.ll | 11 ; RUN: | FileCheck %s -check-prefix=NEON 14 ; RUN: | FileCheck %s -check-prefix=NEON 22 ; NEON-LABEL: test1: 23 ; NEON: vadd.f32 [[D0:d[0-9]+]] 24 ; NEON: vcvt.s32.f32 d0, [[D0]] 34 ; NEON-LABEL: test2: 35 ; NEON: vadd.f32 [[D0:d[0-9]+]] 36 ; NEON: vcvt.u32.f32 d0, [[D0]] 46 ; NEON-LABEL: test3: 47 ; NEON: vcvt.f32.u32 d [all …]
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D | fnmscs.ll | 5 ; RUN: | FileCheck %s -check-prefix=NEON 24 ; NEON-LABEL: t1: 25 ; NEON: vnmla.f32 45 ; NEON-LABEL: t2: 46 ; NEON: vnmla.f32 66 ; NEON-LABEL: t3: 67 ; NEON: vnmla.f64 87 ; NEON-LABEL: t4: 88 ; NEON: vnmla.f64
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D | fmscs.ll | 2 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s -check-prefix=NEON 10 ; NEON-LABEL: t1: 11 ; NEON: vnmls.f32 26 ; NEON-LABEL: t2: 27 ; NEON: vnmls.f64
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D | fnmacs.ll | 2 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s -check-prefix=NEON 10 ; NEON-LABEL: t1: 11 ; NEON: vmls.f32 26 ; NEON-LABEL: t2: 27 ; NEON: vmls.f64
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/external/llvm-project/llvm/test/Transforms/InterleavedAccess/ARM/ |
D | interleaved-accesses.ll | 2 ; RUN: opt < %s -mattr=+neon -interleaved-access -S | FileCheck %s --check-prefix=CHECK-NEON 10 ; CHECK-NEON-LABEL: @load_factor2( 11 ; CHECK-NEON-NEXT: [[TMP1:%.*]] = bitcast <16 x i8>* [[PTR:%.*]] to i8* 12 ; CHECK-NEON-NEXT: [[VLDN:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.arm.neon.vld2.v8i8.p0i8(i8* … 13 ; CHECK-NEON-NEXT: [[TMP2:%.*]] = extractvalue { <8 x i8>, <8 x i8> } [[VLDN]], 1 14 ; CHECK-NEON-NEXT: [[TMP3:%.*]] = extractvalue { <8 x i8>, <8 x i8> } [[VLDN]], 0 15 ; CHECK-NEON-NEXT: ret void 36 ; CHECK-NEON-LABEL: @load_factor3( 37 ; CHECK-NEON-NEXT: [[TMP1:%.*]] = bitcast <6 x i32>* [[PTR:%.*]] to i8* 38 ; CHECK-NEON-NEXT: [[VLDN:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm.neon.vld3.v… [all …]
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/external/llvm/test/MC/ARM/ |
D | neon-mov-vfp.s | 3 …known -show-encoding -mattr=+neon < %s 2>&1 | FileCheck %s --check-prefix=NEON --check-prefix=CHECK 4 …known -show-encoding -mattr=+neon < %s 2>&1 | FileCheck %s --check-prefix=NEON --check-prefix=CHECK 6 @ The 32-bit variants of the NEON scalar move instructions are also available 14 @ VFP-DAG: error: instruction requires: NEON 15 @ VFP-DAG: error: instruction requires: NEON 16 @ NEON-DAG: vmov.8 d22[5], r2 @ encoding: 17 @ NEON-DAG: vmov.16 d3[2], r4 @ encoding: 26 @ VFP-DAG: error: instruction requires: NEON 27 @ VFP-DAG: error: instruction requires: NEON 28 @ NEON-DAG: vmov.s8 r2, d22[5] @ encoding: [all …]
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/external/llvm/test/CodeGen/AArch64/ |
D | aarch64-interleaved-accesses.ll | 1 ; RUN: llc -mtriple=aarch64 -lower-interleaved-accesses=true < %s | FileCheck %s -check-prefix=NEON 4 ; NEON-LABEL: load_factor2: 5 ; NEON: ld2 { v0.8b, v1.8b }, [x0] 16 ; NEON-LABEL: load_factor3: 17 ; NEON: ld3 { v0.4s, v1.4s, v2.4s }, [x0] 29 ; NEON-LABEL: load_factor4: 30 ; NEON: ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0] 42 ; NEON-LABEL: store_factor2: 43 ; NEON: st2 { v0.8b, v1.8b }, [x0] 52 ; NEON-LABEL: store_factor3: [all …]
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/external/llvm-project/clang/lib/CodeGen/ |
D | CGBuiltin.cpp | 5200 { #NameBase, NEON::BI__builtin_neon_ ## NameBase, 0, 0, 0 } 5203 { #NameBase, NEON:: BI__builtin_neon_ ## NameBase, \ 5207 { #NameBase, NEON:: BI__builtin_neon_ ## NameBase, \ 6021 case NEON::BI__builtin_neon_vcled_s64: in EmitCommonNeonSISDBuiltinExpr() 6022 case NEON::BI__builtin_neon_vcled_u64: in EmitCommonNeonSISDBuiltinExpr() 6023 case NEON::BI__builtin_neon_vcles_f32: in EmitCommonNeonSISDBuiltinExpr() 6024 case NEON::BI__builtin_neon_vcled_f64: in EmitCommonNeonSISDBuiltinExpr() 6025 case NEON::BI__builtin_neon_vcltd_s64: in EmitCommonNeonSISDBuiltinExpr() 6026 case NEON::BI__builtin_neon_vcltd_u64: in EmitCommonNeonSISDBuiltinExpr() 6027 case NEON::BI__builtin_neon_vclts_f32: in EmitCommonNeonSISDBuiltinExpr() [all …]
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/external/llvm-project/llvm/test/Analysis/CostModel/ARM/ |
D | reduce-add.ll | 3 … -cost-model -analyze -mtriple=armv8a-linux-gnueabihf < %s | FileCheck %s --check-prefix=NEON-RECIP 5 …e -cost-kind=code-size -mtriple=armv8a-linux-gnueabihf < %s | FileCheck %s --check-prefix=NEON-SIZE 16 ; NEON-RECIP-LABEL: 'reduce_i64' 17 ; NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call i64 @llvm.… 18 ; NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V2 = call i64 @llvm… 19 ; NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 29 for instruction: %V4 = call i64 @llvm… 20 ; NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V8 = call i64 @llvm… 21 ; NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 107 for instruction: %V16 = call i64 @ll… 22 ; NEON-RECIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef 32 ; NEON-SIZE-LABEL: 'reduce_i64' [all …]
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D | shuffle.ll | 3 …model -analyze -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift | FileCheck %s --check-prefix=CHECK-NEON 21 ; CHECK-NEON-LABEL: 'broadcast' 22 ; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v7 = shufflevector <… 23 ; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8 = shufflevector <… 24 ; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v9 = shufflevector <… 25 ; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v10 = shufflevector … 26 ; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v11 = shufflevector … 27 ; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v12 = shufflevector … 28 ; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v13 = shufflevector … 29 ; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v14 = shufflevector … [all …]
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