1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=thumbv7m-arm-none-eabi -mattr=+execute-only,+fp-armv8 | FileCheck %s --check-prefixes=CHECK,VMOVSR 3; RUN: llc < %s -mtriple=thumbv7m-arm-none-eabi -mattr=+execute-only,+fp-armv8,+neon,+neonfp | FileCheck %s --check-prefixes=CHECK,NEON 4 5define arm_aapcs_vfpcc float @foo0(float %a0) local_unnamed_addr { 6; CHECK-LABEL: foo0: 7; CHECK: @ %bb.0: 8; CHECK-NEXT: vcmp.f32 s0, #0 9; CHECK-NEXT: vmov.f32 s2, #5.000000e-01 10; CHECK-NEXT: vmrs APSR_nzcv, fpscr 11; CHECK-NEXT: vmov.f32 s4, #-5.000000e-01 12; CHECK-NEXT: it mi 13; CHECK-NEXT: vmovmi.f32 s2, s4 14; CHECK-NEXT: vmov.f32 s0, s2 15; CHECK-NEXT: bx lr 16 %1 = fcmp nsz olt float %a0, 0.000000e+00 17 %2 = select i1 %1, float -5.000000e-01, float 5.000000e-01 18 ret float %2 19} 20 21define arm_aapcs_vfpcc float @float1(float %a0) local_unnamed_addr { 22; CHECK-LABEL: float1: 23; CHECK: @ %bb.0: @ %.end 24; CHECK-NEXT: vmov.f32 s2, #1.000000e+00 25; CHECK-NEXT: vmov.f32 s4, #5.000000e-01 26; CHECK-NEXT: vmov.f32 s6, #-5.000000e-01 27; CHECK-NEXT: vcmp.f32 s2, s0 28; CHECK-NEXT: vmrs APSR_nzcv, fpscr 29; CHECK-NEXT: vselgt.f32 s0, s6, s4 30; CHECK-NEXT: bx lr 31 br i1 undef, label %.end, label %1 32 33 %2 = fcmp nsz olt float %a0, 1.000000e+00 34 %3 = select i1 %2, float -5.000000e-01, float 5.000000e-01 35 br label %.end 36 37.end: 38 %4 = phi float [ undef, %0 ], [ %3, %1] 39 ret float %4 40} 41 42define arm_aapcs_vfpcc float @float128(float %a0) local_unnamed_addr { 43; VMOVSR-LABEL: float128: 44; VMOVSR: @ %bb.0: 45; VMOVSR-NEXT: mov.w r0, #1124073472 46; VMOVSR-NEXT: vmov.f32 s4, #5.000000e-01 47; VMOVSR-NEXT: vmov s2, r0 48; VMOVSR-NEXT: vmov.f32 s6, #-5.000000e-01 49; VMOVSR-NEXT: vcmp.f32 s2, s0 50; VMOVSR-NEXT: vmrs APSR_nzcv, fpscr 51; VMOVSR-NEXT: vselgt.f32 s0, s6, s4 52; VMOVSR-NEXT: bx lr 53; 54; NEON-LABEL: float128: 55; NEON: @ %bb.0: 56; NEON-NEXT: mov.w r0, #1124073472 57; NEON-NEXT: vmov.f32 s2, #5.000000e-01 58; NEON-NEXT: vmov d3, r0, r0 59; NEON-NEXT: vmov.f32 s4, #-5.000000e-01 60; NEON-NEXT: vcmp.f32 s6, s0 61; NEON-NEXT: vmrs APSR_nzcv, fpscr 62; NEON-NEXT: vselgt.f32 s0, s4, s2 63; NEON-NEXT: bx lr 64 %1 = fcmp nsz olt float %a0, 128.000000e+00 65 %2 = select i1 %1, float -5.000000e-01, float 5.000000e-01 66 ret float %2 67} 68 69define arm_aapcs_vfpcc double @double1(double %a0) local_unnamed_addr { 70; CHECK-LABEL: double1: 71; CHECK: @ %bb.0: 72; CHECK-NEXT: vmov.f64 d18, #1.000000e+00 73; CHECK-NEXT: vcmp.f64 d18, d0 74; CHECK-NEXT: vmrs APSR_nzcv, fpscr 75; CHECK-NEXT: vmov.f64 d16, #5.000000e-01 76; CHECK-NEXT: vmov.f64 d17, #-5.000000e-01 77; CHECK-NEXT: vselgt.f64 d0, d17, d16 78; CHECK-NEXT: bx lr 79 %1 = fcmp nsz olt double %a0, 1.000000e+00 80 %2 = select i1 %1, double -5.000000e-01, double 5.000000e-01 81 ret double %2 82} 83 84define arm_aapcs_vfpcc double @double128(double %a0) local_unnamed_addr { 85; CHECK-LABEL: double128: 86; CHECK: @ %bb.0: 87; CHECK-NEXT: movs r0, #0 88; CHECK-NEXT: movs r1, #0 89; CHECK-NEXT: movt r0, #16480 90; CHECK-NEXT: vmov.f64 d16, #5.000000e-01 91; CHECK-NEXT: vmov d18, r1, r0 92; CHECK-NEXT: vcmp.f64 d18, d0 93; CHECK-NEXT: vmrs APSR_nzcv, fpscr 94; CHECK-NEXT: vmov.f64 d17, #-5.000000e-01 95; CHECK-NEXT: vselgt.f64 d0, d17, d16 96; CHECK-NEXT: bx lr 97 %1 = fcmp nsz olt double %a0, 128.000000e+00 98 %2 = select i1 %1, double -5.000000e-01, double 5.000000e-01 99 ret double %2 100} 101