| /external/llvm/lib/Target/ARM/ |
| D | ARMFrameLowering.cpp | 1128 unsigned NextReg = ARM::D8; in emitAlignedDPRCS2Spills() local
1133 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1139 .addReg(NextReg) in emitAlignedDPRCS2Spills()
1141 NextReg += 4; in emitAlignedDPRCS2Spills()
1147 unsigned R4BaseReg = NextReg; in emitAlignedDPRCS2Spills()
1151 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1155 .addReg(ARM::R4).addImm(16).addReg(NextReg) in emitAlignedDPRCS2Spills()
1157 NextReg += 4; in emitAlignedDPRCS2Spills()
1163 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1168 NextReg += 2; in emitAlignedDPRCS2Spills()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMFrameLowering.cpp | 1236 unsigned NextReg = ARM::D8; in emitAlignedDPRCS2Spills() local
1241 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1247 .addReg(NextReg) in emitAlignedDPRCS2Spills()
1250 NextReg += 4; in emitAlignedDPRCS2Spills()
1256 unsigned R4BaseReg = NextReg; in emitAlignedDPRCS2Spills()
1260 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1266 .addReg(NextReg) in emitAlignedDPRCS2Spills()
1269 NextReg += 4; in emitAlignedDPRCS2Spills()
1275 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1283 NextReg += 2; in emitAlignedDPRCS2Spills()
[all …]
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMFrameLowering.cpp | 1243 unsigned NextReg = ARM::D8; in emitAlignedDPRCS2Spills() local
1248 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1254 .addReg(NextReg) in emitAlignedDPRCS2Spills()
1257 NextReg += 4; in emitAlignedDPRCS2Spills()
1263 unsigned R4BaseReg = NextReg; in emitAlignedDPRCS2Spills()
1267 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1273 .addReg(NextReg) in emitAlignedDPRCS2Spills()
1276 NextReg += 4; in emitAlignedDPRCS2Spills()
1282 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1290 NextReg += 2; in emitAlignedDPRCS2Spills()
[all …]
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 913 unsigned NextReg = CSI[i + 1].getReg(); in computeCalleeSaveRegisterPairs() local
914 if ((RPI.IsGPR && AArch64::GPR64RegClass.contains(NextReg)) || in computeCalleeSaveRegisterPairs()
915 (!RPI.IsGPR && AArch64::FPR64RegClass.contains(NextReg))) in computeCalleeSaveRegisterPairs()
916 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCMIPeephole.cpp | 1082 unsigned NextReg = SrcReg; in getSrcVReg() local
1085 NextReg = getIncomingRegForBlock(Inst, BB1); in getSrcVReg()
1090 NextReg = Inst->getOperand(1).getReg(); in getSrcVReg()
1091 if (NextReg == SrcReg || !Register::isVirtualRegister(NextReg)) in getSrcVReg()
1093 SrcReg = NextReg; in getSrcVReg()
|
| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCMIPeephole.cpp | 1107 unsigned NextReg = SrcReg; in getSrcVReg() local
1110 NextReg = getIncomingRegForBlock(Inst, BB1); in getSrcVReg()
1115 NextReg = Inst->getOperand(1).getReg(); in getSrcVReg()
1116 if (NextReg == SrcReg || !Register::isVirtualRegister(NextReg)) in getSrcVReg()
1118 SrcReg = NextReg; in getSrcVReg()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 1982 unsigned NextReg = CSI[i + 1].getReg(); in computeCalleeSaveRegisterPairs() local
1985 if (AArch64::GPR64RegClass.contains(NextReg) && in computeCalleeSaveRegisterPairs()
1986 !invalidateRegisterPairing(RPI.Reg1, NextReg, IsWindows, NeedsWinCFI, in computeCalleeSaveRegisterPairs()
1988 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
1991 if (AArch64::FPR64RegClass.contains(NextReg) && in computeCalleeSaveRegisterPairs()
1992 !invalidateWindowsRegisterPairing(RPI.Reg1, NextReg, NeedsWinCFI)) in computeCalleeSaveRegisterPairs()
1993 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
1996 if (AArch64::FPR128RegClass.contains(NextReg)) in computeCalleeSaveRegisterPairs()
1997 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 2147 unsigned NextReg = CSI[i + RegInc].getReg(); in computeCalleeSaveRegisterPairs() local
2151 if (AArch64::GPR64RegClass.contains(NextReg) && in computeCalleeSaveRegisterPairs()
2152 !invalidateRegisterPairing(RPI.Reg1, NextReg, IsWindows, in computeCalleeSaveRegisterPairs()
2154 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
2157 if (AArch64::FPR64RegClass.contains(NextReg) && in computeCalleeSaveRegisterPairs()
2158 !invalidateWindowsRegisterPairing(RPI.Reg1, NextReg, NeedsWinCFI, in computeCalleeSaveRegisterPairs()
2160 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
2163 if (AArch64::FPR128RegClass.contains(NextReg)) in computeCalleeSaveRegisterPairs()
2164 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
|
| /external/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64InstructionSelector.cpp | 1278 Register NextReg = MI->getOperand(1).getReg(); in getTestBitReg() local
1280 if (!NextReg.isValid() || !MRI.hasOneNonDBGUse(NextReg)) in getTestBitReg()
1284 Reg = NextReg; in getTestBitReg()
1328 Register NextReg; in getTestBitReg() local
1336 NextReg = TestReg; in getTestBitReg()
1342 NextReg = TestReg; in getTestBitReg()
1349 NextReg = TestReg; in getTestBitReg()
1357 NextReg = TestReg; in getTestBitReg()
1372 NextReg = TestReg; in getTestBitReg()
1377 if (!NextReg.isValid()) in getTestBitReg()
[all …]
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceInstARM32.cpp | 1433 const Variable *NextReg = getStackReg(i); in emitUsingForm() local
1434 assert(NextReg->hasReg()); in emitUsingForm()
1436 BaseReg = NextReg; in emitUsingForm()
1439 isAssignedConsecutiveRegisters(Reg, NextReg)) { in emitUsingForm()
1443 BaseReg = NextReg; in emitUsingForm()
1446 Reg = NextReg; in emitUsingForm()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 2230 unsigned NextReg, NextRegNum, NextRegWidth; in ParseRegList() local
2232 if (!ParseAMDGPURegister(NextRegKind, NextReg, NextRegNum, NextRegWidth)) in ParseRegList()
2238 if (!AddNextRegisterToList(Reg, RegWidth, RegKind, NextReg)) in ParseRegList()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 2417 unsigned NextReg, NextRegNum, NextRegWidth; in ParseRegList() local
2420 if (!ParseAMDGPURegister(NextRegKind, NextReg, in ParseRegList()
2433 if (!AddNextRegisterToList(Reg, RegWidth, RegKind, NextReg, Loc)) in ParseRegList()
|
| /external/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 6141 int NextReg = nextReg(((MipsOperand &)*Operands[1]).getGPR32Reg()); in ConvertXWPOperands() local
6142 Inst.addOperand(MCOperand::createReg(NextReg)); in ConvertXWPOperands()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 5949 int NextReg = nextReg(((MipsOperand &)*Operands[1]).getGPR32Reg()); in ConvertXWPOperands() local
5950 Inst.addOperand(MCOperand::createReg(NextReg)); in ConvertXWPOperands()
|