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Searched refs:ORI (Results 1 – 25 of 68) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/RISCV/
Dmachineoutliner.mir35 $x11 = ORI $x11, 1023
53 $x11 = ORI $x11, 1023
71 $x11 = ORI $x11, 1023
89 $x11 = ORI $x11, 1023
107 $x11 = ORI $x11, 1023
125 $x11 = ORI $x11, 1023
/external/pcre/dist2/src/sljit/
DsljitNativePPC_64.c52 return push_inst(compiler, ORI | S(TMP_ZERO) | A(reg) | IMM(imm)); in load_immediate()
56 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm)) : SLJIT_SUCCESS; in load_immediate()
74 FAIL_IF(push_inst(compiler, ORI | S(reg) | A(reg) | IMM(tmp >> 32))); in load_immediate()
86 return push_inst(compiler, ORI | S(reg) | A(reg) | tmp2); in load_immediate()
93 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(tmp2)) : SLJIT_SUCCESS; in load_immediate()
104 FAIL_IF(push_inst(compiler, ORI | S(reg) | A(reg) | (tmp2 >> 48))); in load_immediate()
110 FAIL_IF(push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm >> 32))); in load_immediate()
113 return push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm)); in load_immediate()
343 return push_inst(compiler, ORI | S(src1) | A(dst) | compiler->imm); in emit_single_op()
351 FAIL_IF(push_inst(compiler, ORI | S(src1) | A(dst) | IMM(compiler->imm))); in emit_single_op()
[all …]
DsljitNativePPC_32.c35 return push_inst(compiler, ORI | S(TMP_ZERO) | A(reg) | IMM(imm)); in load_immediate()
38 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm)) : SLJIT_SUCCESS; in load_immediate()
194 return push_inst(compiler, ORI | S(src1) | A(dst) | compiler->imm); in emit_single_op()
202 FAIL_IF(push_inst(compiler, ORI | S(src1) | A(dst) | IMM(compiler->imm))); in emit_single_op()
255 return push_inst(compiler, ORI | S(reg) | A(reg) | IMM(init_value)); in emit_const()
264 SLJIT_ASSERT((inst[0] & 0xfc1f0000) == ADDIS && (inst[1] & 0xfc000000) == ORI); in sljit_set_jump_addr()
DsljitNativeMIPS_64.c38 return push_inst(compiler, ORI | SA(0) | TA(dst_ar) | IMM(imm), dst_ar); in load_immediate()
45 …return (imm & 0xffff) ? push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(imm), dst_ar) : SL… in load_immediate()
81 FAIL_IF(push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(uimm >> 32), dst_ar)); in load_immediate()
89 …return !(imm & 0xffff) ? SLJIT_SUCCESS : push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(i… in load_immediate()
114 FAIL_IF(push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(uimm >> 48), dst_ar)); in load_immediate()
118 …return !(imm & 0xffff) ? SLJIT_SUCCESS : push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(i… in load_immediate()
237 …FAIL_IF(push_inst(compiler, ORI | SA(0) | T(dst) | IMM((op & SLJIT_I32_OP) ? 32 : 64), UNMOVABLE_I… in emit_single_op()
262 FAIL_IF(push_inst(compiler, ORI | S(src1) | TA(OTHER_FLAG) | IMM(src2), OTHER_FLAG)); in emit_single_op()
303 FAIL_IF(push_inst(compiler, ORI | S(src1) | TA(EQUAL_FLAG) | IMM(src2), EQUAL_FLAG)); in emit_single_op()
491 EMIT_LOGICAL(ORI, OR); in emit_single_op()
[all …]
DsljitNativeMIPS_32.c32 return push_inst(compiler, ORI | SA(0) | TA(dst_ar) | IMM(imm), dst_ar); in load_immediate()
38 …return (imm & 0xffff) ? push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(imm), dst_ar) : SL… in load_immediate()
146 FAIL_IF(push_inst(compiler, ORI | SA(0) | T(dst) | IMM(32), UNMOVABLE_INS)); in emit_single_op()
171 FAIL_IF(push_inst(compiler, ORI | S(src1) | TA(OTHER_FLAG) | IMM(src2), OTHER_FLAG)); in emit_single_op()
212 FAIL_IF(push_inst(compiler, ORI | S(src1) | TA(EQUAL_FLAG) | IMM(src2), EQUAL_FLAG)); in emit_single_op()
395 EMIT_LOGICAL(ORI, OR); in emit_single_op()
422 return push_inst(compiler, ORI | S(dst) | T(dst) | IMM(init_value), DR(dst)); in emit_const()
431 SLJIT_ASSERT((inst[0] & 0xffe00000) == LUI && (inst[1] & 0xfc000000) == ORI); in sljit_set_jump_addr()
DsljitNativeMIPS_common.c234 #define ORI (HI(13)) macro
484 inst[1] = ORI | S(reg) | T(reg) | IMM((addr >> 16) & 0xffff); in put_label_set()
490 inst[1] = ORI | S(reg) | T(reg) | IMM((addr >> 32) & 0xffff); in put_label_set()
492 inst[3] = ORI | S(reg) | T(reg) | IMM((addr >> 16) & 0xffff); in put_label_set()
497 inst[1] = ORI | S(reg) | T(reg) | IMM(addr & 0xffff); in put_label_set()
648 SLJIT_ASSERT((buf_ptr[0] & 0xffe00000) == LUI && (buf_ptr[1] & 0xfc000000) == ORI); in sljit_generate_code()
DsljitNativePPC_common.c203 #define ORI (HI(24)) macro
361 inst[0] = ORI | S(TMP_ZERO) | A(reg) | IMM(addr >> 32); in put_label_set()
365 inst[1] = ORI | S(reg) | A(reg) | IMM((addr >> 32) & 0xffff); in put_label_set()
374 inst[1] = ORI | S(reg) | A(reg) | IMM(addr & 0xffff); in put_label_set()
584 SLJIT_ASSERT((buf_ptr[0] & 0xfc1f0000) == ADDIS && (buf_ptr[1] & 0xfc000000) == ORI); in sljit_generate_code()
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dexpand-isel-8.mir53 ; CHECK: $r5 = ORI $r4, 0
54 ; CHECK: $r3 = ORI $r5, 0
55 ; CHECK: $r4 = ORI $r5, 0
Dfixup-kill-dead-flag-crash.mir34 %3:gprc = ORI killed %2:gprc, 1
Dexpand-isel-7.mir51 ; CHECK: $r5 = ORI $r4, 0
Dexpand-isel-6.mir51 ; CHECK: $r3 = ORI $r0, 0
Dexpand-isel-3.mir51 ; CHECK: $r3 = ORI $r0, 0
Dexpand-isel-2.mir51 ; CHECK: $r3 = ORI $r4, 0
Dsink-down-more-instructions-1.mir319 ; CHECK: [[ORI:%[0-9]+]]:gprc = ORI [[LIS]], 34953
349 ; CHECK: [[ORI1:%[0-9]+]]:gprc = ORI killed [[LIS1]], 34953
374 ; CHECK: [[MULHWU1:%[0-9]+]]:gprc = MULHWU [[COPY10]], [[ORI]]
470 %57:gprc = ORI %56, 34953
500 %83:gprc = ORI killed %82, 34953
Dexpand-isel-4.mir52 ; CHECK: $r0 = ORI killed $r5, 0
Dexpand-isel-liveness.mir74 ; CHECK: $r3 = ORI killed $r0, 0
Dsink-down-more-instructions-regpressure-high.mir503 ; CHECK: [[ORI:%[0-9]+]]:gprc = ORI [[LIS]], 34953
539 ; CHECK: [[MULHWU:%[0-9]+]]:gprc = MULHWU [[COPY9]], [[ORI]]
678 %70:gprc = ORI %69, 34953
/external/llvm-project/llvm/lib/Transforms/IPO/
DPartialInlining.cpp173 : ORI() {} in FunctionOutliningMultiRegionInfo()
188 SmallVector<OutlineRegionInfo, 4> ORI; member
551 OutliningInfo->ORI.push_back(RegInfo); in computeOutliningColdRegionsInfo()
1029 OI->ORI) { in FunctionCloner()
1041 ClonedOMRI->ORI.push_back(MappedRegionInfo); in FunctionCloner()
1138 if (ClonedOMRI->ORI.empty()) in doMultiRegionFunctionOutlining()
1155 ClonedOMRI->ORI) { in doMultiRegionFunctionOutlining()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/IPO/
DPartialInlining.cpp181 : ORI() {} in FunctionOutliningMultiRegionInfo()
196 SmallVector<OutlineRegionInfo, 4> ORI; member
539 OutliningInfo->ORI.push_back(RegInfo); in computeOutliningColdRegionsInfo()
1004 OI->ORI) { in FunctionCloner()
1016 ClonedOMRI->ORI.push_back(MappedRegionInfo); in FunctionCloner()
1114 if (ClonedOMRI->ORI.empty()) in doMultiRegionFunctionOutlining()
1131 ClonedOMRI->ORI) { in doMultiRegionFunctionOutlining()
/external/llvm/lib/Target/PowerPC/
DPPCFrameLowering.cpp351 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
355 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
377 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
765 : PPC::ORI ); in emitPrologue()
1141 : PPC::ORI ); in emitEpilogue()
1829 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; in eliminateCallFramePseudoInstr()
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenDAGISel.inc23272 /* 57207*/ OPC_MorphNodeTo1, TARGET_VAL(PPC::ORI), 0,
23275 … // Dst: (ORI:{ *:[i32] } i32:{ *:[i32] }:$src1, (LO16:{ *:[i32] } (imm:{ *:[i32] }):$src2))
23311 /* 57281*/ OPC_EmitNode1, TARGET_VAL(PPC::ORI), 0,
23318 …// Dst: (ORIS:{ *:[i32] } (ORI:{ *:[i32] } ?:{ *:[i32] }:$in, (LO16:{ *:[i32] } (imm:{ *:[i32] }):…
28409 /* 68356*/ OPC_MorphNodeTo1, TARGET_VAL(PPC::ORI), 0,
28412 …// Dst: (ORI:{ *:[i32] } (LIS:{ *:[i32] } (HI16:{ *:[i32] } (imm:{ *:[i32] }):$imm)), (LO16:{ *:[i…
30815 /* 73653*/ OPC_EmitNode1, TARGET_VAL(PPC::ORI), 0,
30828 /* 73705*/ OPC_EmitNode1, TARGET_VAL(PPC::ORI), 0,
30843 /* 73763*/ OPC_EmitNode1, TARGET_VAL(PPC::ORI), 0,
30856 /* 73815*/ OPC_EmitNode1, TARGET_VAL(PPC::ORI), 0,
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCFrameLowering.cpp386 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
390 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
412 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
850 : PPC::ORI ); in emitPrologue()
1416 : PPC::ORI ); in emitEpilogue()
2322 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; in eliminateCallFramePseudoInstr()
DPPCExpandISEL.cpp484 TII->get(isISEL8(*MI) ? PPC::ORI8 : PPC::ORI)) in populateBlocks()
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCExpandISEL.cpp455 TII->get(isISEL8(*MI) ? PPC::ORI8 : PPC::ORI)) in populateBlocks()
DPPCFrameLowering.cpp664 : PPC::ORI ); in emitPrologue()
1253 BuildMI(MBB, MBBI, DL, TII.get(isPPC64 ? PPC::ORI8 : PPC::ORI), TempReg) in inlineStackProbe()
1529 : PPC::ORI ); in emitEpilogue()
2401 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; in eliminateCallFramePseudoInstr()

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