1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -o - %s -verify-machineinstrs \ 3# RUN: -run-pass=machine-sink | FileCheck %s 4 5--- | 6 ; ModuleID = 'sink-down-more-instructions-1.ll' 7 source_filename = "sink-down-more-instructions-1.c" 8 target datalayout = "e-m:e-i64:64-n32:64" 9 target triple = "powerpc64le-unknown-linux-gnu" 10 11 ; Function Attrs: nofree norecurse nounwind 12 define dso_local signext i32 @foo(i32 signext %0, i32 signext %1, i32* nocapture readonly %2, i32* nocapture %3, i32 signext %4) local_unnamed_addr #0 { 13 %6 = icmp sgt i32 %4, 0 14 br i1 %6, label %7, label %37 15 16 7: ; preds = %5 17 %8 = zext i32 %4 to i64 18 %9 = icmp eq i32 %4, 1 19 br i1 %9, label %17, label %10 20 21 10: ; preds = %7 22 %11 = and i64 %8, 4294967294 23 %scevgep20 = getelementptr i32, i32* %2, i64 -2 24 %scevgep2021 = bitcast i32* %scevgep20 to i8* 25 %scevgep22 = getelementptr i32, i32* %3, i64 -2 26 %scevgep2223 = bitcast i32* %scevgep22 to i8* 27 %12 = add nsw i64 %11, -2 28 %13 = lshr i64 %12, 1 29 %14 = add nuw i64 %13, 1 30 call void @llvm.set.loop.iterations.i64(i64 %14) 31 br label %38 32 33 15: ; preds = %74 34 %16 = add nuw i32 %tmp18, 102 35 br label %17 36 37 17: ; preds = %15, %7 38 %18 = phi i64 [ 0, %7 ], [ %78, %15 ] 39 %19 = phi i32 [ 100, %7 ], [ %16, %15 ] 40 %20 = phi i32 [ 0, %7 ], [ %66, %15 ] 41 %21 = and i64 %8, 1 42 %22 = icmp eq i64 %21, 0 43 br i1 %22, label %37, label %23 44 45 23: ; preds = %17 46 %24 = getelementptr inbounds i32, i32* %2, i64 %18 47 %25 = load i32, i32* %24, align 4, !tbaa !2 48 %26 = add nsw i32 %25, %20 49 switch i32 %0, label %30 [ 50 i32 1, label %27 51 i32 3, label %33 52 ] 53 54 27: ; preds = %23 55 %28 = trunc i64 %18 to i32 56 %29 = shl i32 %28, 1 57 br label %33 58 59 30: ; preds = %23 60 %31 = trunc i64 %18 to i32 61 %32 = urem i32 %31, 30 62 br label %33 63 64 33: ; preds = %30, %27, %23 65 %34 = phi i32 [ %32, %30 ], [ %29, %27 ], [ %19, %23 ] 66 %35 = add nsw i32 %34, %26 67 %36 = getelementptr inbounds i32, i32* %3, i64 %18 68 store i32 %35, i32* %36, align 4, !tbaa !2 69 br label %37 70 71 37: ; preds = %33, %17, %5 72 ret i32 undef 73 74 38: ; preds = %74, %10 75 %39 = phi i64 [ 0, %10 ], [ %78, %74 ] 76 %40 = phi i32 [ 0, %10 ], [ %66, %74 ] 77 %41 = phi i8* [ %scevgep2021, %10 ], [ %45, %74 ] 78 %42 = phi i8* [ %scevgep2223, %10 ], [ %43, %74 ] 79 %43 = getelementptr i8, i8* %42, i64 8 80 %44 = bitcast i8* %43 to i32* 81 %45 = getelementptr i8, i8* %41, i64 8 82 %46 = bitcast i8* %45 to i32* 83 %lsr19 = trunc i64 %39 to i32 84 %47 = udiv i32 %lsr19, 30 85 %48 = mul nsw i32 %47, -30 86 %49 = zext i32 %48 to i64 87 %50 = add nuw nsw i64 %49, 1 88 %51 = load i32, i32* %46, align 4, !tbaa !2 89 %52 = add nsw i32 %51, %40 90 switch i32 %0, label %58 [ 91 i32 1, label %53 92 i32 3, label %56 93 ] 94 95 53: ; preds = %38 96 %54 = trunc i64 %39 to i32 97 %55 = shl i32 %54, 1 98 br label %60 99 100 56: ; preds = %38 101 %57 = add nuw nsw i32 %lsr19, 100 102 br label %60 103 104 58: ; preds = %38 105 %59 = add i64 %39, %49 106 %tmp15 = trunc i64 %59 to i32 107 br label %60 108 109 60: ; preds = %58, %56, %53 110 %61 = phi i32 [ %tmp15, %58 ], [ %57, %56 ], [ %55, %53 ] 111 %62 = add nsw i32 %61, %52 112 store i32 %62, i32* %44, align 4, !tbaa !2 113 %63 = or i64 %39, 1 114 %64 = getelementptr i8, i8* %45, i64 4 115 %uglygep1112.cast = bitcast i8* %64 to i32* 116 %65 = load i32, i32* %uglygep1112.cast, align 4, !tbaa !2 117 %66 = add nsw i32 %65, %52 118 switch i32 %0, label %72 [ 119 i32 1, label %69 120 i32 3, label %67 121 ] 122 123 67: ; preds = %60 124 %68 = add nuw nsw i32 %lsr19, 101 125 br label %74 126 127 69: ; preds = %60 128 %70 = trunc i64 %63 to i32 129 %71 = shl i32 %70, 1 130 br label %74 131 132 72: ; preds = %60 133 %73 = add i64 %39, %50 134 %tmp = trunc i64 %73 to i32 135 br label %74 136 137 74: ; preds = %72, %69, %67 138 %75 = phi i32 [ %tmp, %72 ], [ %68, %67 ], [ %71, %69 ] 139 %76 = add nsw i32 %75, %66 140 %77 = getelementptr i8, i8* %43, i64 4 141 %uglygep78.cast = bitcast i8* %77 to i32* 142 store i32 %76, i32* %uglygep78.cast, align 4, !tbaa !2 143 %78 = add nuw nsw i64 %39, 2 144 %79 = add i64 %78, -2 145 %tmp18 = trunc i64 %79 to i32 146 %80 = call i1 @llvm.loop.decrement.i64(i64 1) 147 br i1 %80, label %38, label %15 148 } 149 150 ; Function Attrs: noduplicate nounwind 151 declare void @llvm.set.loop.iterations.i64(i64) #1 152 153 ; Function Attrs: noduplicate nounwind 154 declare i1 @llvm.loop.decrement.i64(i64) #1 155 156 attributes #0 = { nofree norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector,-spe" "unsafe-fp-math"="false" "use-soft-float"="false" } 157 attributes #1 = { noduplicate nounwind } 158 159 !llvm.module.flags = !{!0} 160 !llvm.ident = !{!1} 161 162 !0 = !{i32 1, !"wchar_size", i32 4} 163 !1 = !{!"clang version 12.0.0"} 164 !2 = !{!3, !3, i64 0} 165 !3 = !{!"int", !4, i64 0} 166 !4 = !{!"omnipotent char", !5, i64 0} 167 !5 = !{!"Simple C/C++ TBAA"} 168 169... 170--- 171name: foo 172alignment: 16 173tracksRegLiveness: true 174registers: 175 - { id: 0, class: g8rc } 176 - { id: 1, class: g8rc } 177 - { id: 2, class: g8rc } 178 - { id: 3, class: gprc } 179 - { id: 4, class: g8rc } 180 - { id: 5, class: gprc } 181 - { id: 6, class: gprc } 182 - { id: 7, class: gprc } 183 - { id: 8, class: gprc_and_gprc_nor0 } 184 - { id: 9, class: gprc } 185 - { id: 10, class: gprc } 186 - { id: 11, class: g8rc_and_g8rc_nox0 } 187 - { id: 12, class: gprc } 188 - { id: 13, class: g8rc_and_g8rc_nox0 } 189 - { id: 14, class: g8rc_and_g8rc_nox0 } 190 - { id: 15, class: g8rc_and_g8rc_nox0 } 191 - { id: 16, class: g8rc_and_g8rc_nox0 } 192 - { id: 17, class: g8rc_and_g8rc_nox0 } 193 - { id: 18, class: gprc_and_gprc_nor0 } 194 - { id: 19, class: g8rc } 195 - { id: 20, class: g8rc } 196 - { id: 21, class: gprc } 197 - { id: 22, class: gprc_and_gprc_nor0 } 198 - { id: 23, class: gprc } 199 - { id: 24, class: gprc } 200 - { id: 25, class: gprc } 201 - { id: 26, class: g8rc } 202 - { id: 27, class: gprc } 203 - { id: 28, class: gprc } 204 - { id: 29, class: gprc } 205 - { id: 30, class: gprc } 206 - { id: 31, class: gprc } 207 - { id: 32, class: g8rc } 208 - { id: 33, class: gprc_and_gprc_nor0 } 209 - { id: 34, class: g8rc } 210 - { id: 35, class: g8rc } 211 - { id: 36, class: g8rc_and_g8rc_nox0 } 212 - { id: 37, class: g8rc_and_g8rc_nox0 } 213 - { id: 38, class: g8rc } 214 - { id: 39, class: gprc } 215 - { id: 40, class: gprc } 216 - { id: 41, class: crrc } 217 - { id: 42, class: g8rc } 218 - { id: 43, class: gprc } 219 - { id: 44, class: gprc } 220 - { id: 45, class: g8rc } 221 - { id: 46, class: g8rc } 222 - { id: 47, class: crrc } 223 - { id: 48, class: g8rc } 224 - { id: 49, class: gprc } 225 - { id: 50, class: g8rc_and_g8rc_nox0 } 226 - { id: 51, class: g8rc } 227 - { id: 52, class: g8rc_and_g8rc_nox0 } 228 - { id: 53, class: g8rc } 229 - { id: 54, class: gprc } 230 - { id: 55, class: g8rc_and_g8rc_nox0 } 231 - { id: 56, class: gprc } 232 - { id: 57, class: gprc } 233 - { id: 58, class: gprc } 234 - { id: 59, class: gprc } 235 - { id: 60, class: gprc } 236 - { id: 61, class: g8rc } 237 - { id: 62, class: g8rc } 238 - { id: 63, class: crrc } 239 - { id: 64, class: crrc } 240 - { id: 65, class: gprc } 241 - { id: 66, class: g8rc } 242 - { id: 67, class: gprc } 243 - { id: 68, class: gprc } 244 - { id: 69, class: crrc } 245 - { id: 70, class: crrc } 246 - { id: 71, class: gprc } 247 - { id: 72, class: g8rc } 248 - { id: 73, class: gprc } 249 - { id: 74, class: gprc_and_gprc_nor0 } 250 - { id: 75, class: crbitrc } 251 - { id: 76, class: g8rc } 252 - { id: 77, class: gprc } 253 - { id: 78, class: crrc } 254 - { id: 79, class: crrc } 255 - { id: 80, class: gprc } 256 - { id: 81, class: gprc } 257 - { id: 82, class: gprc } 258 - { id: 83, class: gprc } 259 - { id: 84, class: gprc } 260 - { id: 85, class: gprc } 261 - { id: 86, class: gprc } 262 - { id: 87, class: gprc } 263 - { id: 88, class: g8rc } 264 - { id: 89, class: g8rc } 265 - { id: 90, class: g8rc } 266 - { id: 91, class: gprc } 267 - { id: 92, class: gprc_nor0 } 268 - { id: 93, class: gprc } 269 - { id: 94, class: gprc_nor0 } 270 - { id: 95, class: crrc } 271liveins: 272 - { reg: '$x3', virtual-reg: '%34' } 273 - { reg: '$x5', virtual-reg: '%36' } 274 - { reg: '$x6', virtual-reg: '%37' } 275 - { reg: '$x7', virtual-reg: '%38' } 276frameInfo: 277 maxAlignment: 1 278machineFunctionInfo: {} 279body: | 280 ; CHECK-LABEL: name: foo 281 ; CHECK: bb.0 (%ir-block.5): 282 ; CHECK: successors: %bb.1(0x50000000), %bb.8(0x30000000) 283 ; CHECK: liveins: $x3, $x5, $x6, $x7 284 ; CHECK: [[COPY:%[0-9]+]]:g8rc = COPY $x7 285 ; CHECK: [[COPY1:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x6 286 ; CHECK: [[COPY2:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x5 287 ; CHECK: [[COPY3:%[0-9]+]]:g8rc = COPY $x3 288 ; CHECK: [[COPY4:%[0-9]+]]:gprc = COPY [[COPY]].sub_32 289 ; CHECK: [[CMPWI:%[0-9]+]]:crrc = CMPWI [[COPY4]], 1 290 ; CHECK: BCC 12, killed [[CMPWI]], %bb.8 291 ; CHECK: B %bb.1 292 ; CHECK: bb.1 (%ir-block.7): 293 ; CHECK: successors: %bb.18(0x40000000), %bb.2(0x40000000) 294 ; CHECK: [[COPY5:%[0-9]+]]:gprc = COPY [[COPY3]].sub_32 295 ; CHECK: [[DEF:%[0-9]+]]:g8rc = IMPLICIT_DEF 296 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF]], [[COPY4]], %subreg.sub_32 297 ; CHECK: [[RLDICL:%[0-9]+]]:g8rc = RLDICL killed [[INSERT_SUBREG]], 0, 32 298 ; CHECK: [[CMPLWI:%[0-9]+]]:crrc = CMPLWI [[COPY4]], 1 299 ; CHECK: [[CMPLWI1:%[0-9]+]]:crrc = CMPLWI [[COPY5]], 3 300 ; CHECK: BCC 68, killed [[CMPLWI]], %bb.2 301 ; CHECK: bb.18: 302 ; CHECK: successors: %bb.4(0x80000000) 303 ; CHECK: [[LI:%[0-9]+]]:gprc = LI 0 304 ; CHECK: [[LI1:%[0-9]+]]:gprc = LI 100 305 ; CHECK: [[LI8_:%[0-9]+]]:g8rc = LI8 0 306 ; CHECK: B %bb.4 307 ; CHECK: bb.2 (%ir-block.10): 308 ; CHECK: successors: %bb.9(0x80000000) 309 ; CHECK: [[RLWINM8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = RLWINM8 [[RLDICL]], 0, 0, 30 310 ; CHECK: [[ADDI8_:%[0-9]+]]:g8rc = ADDI8 [[COPY2]], -8 311 ; CHECK: [[ADDI8_1:%[0-9]+]]:g8rc = ADDI8 [[COPY1]], -8 312 ; CHECK: [[ADDI8_2:%[0-9]+]]:g8rc = nsw ADDI8 killed [[RLWINM8_]], -2 313 ; CHECK: [[RLDICL1:%[0-9]+]]:g8rc_and_g8rc_nox0 = RLDICL [[ADDI8_2]], 63, 1 314 ; CHECK: [[ADDI8_3:%[0-9]+]]:g8rc = nuw ADDI8 killed [[RLDICL1]], 1 315 ; CHECK: MTCTR8loop killed [[ADDI8_3]], implicit-def dead $ctr8 316 ; CHECK: [[LI2:%[0-9]+]]:gprc = LI 0 317 ; CHECK: [[LI8_1:%[0-9]+]]:g8rc = LI8 0 318 ; CHECK: [[LIS:%[0-9]+]]:gprc = LIS 34952 319 ; CHECK: [[ORI:%[0-9]+]]:gprc = ORI [[LIS]], 34953 320 ; CHECK: [[DEF1:%[0-9]+]]:g8rc = IMPLICIT_DEF 321 ; CHECK: [[CMPLWI2:%[0-9]+]]:crrc = CMPLWI [[COPY5]], 1 322 ; CHECK: B %bb.9 323 ; CHECK: bb.3 (%ir-block.15): 324 ; CHECK: successors: %bb.4(0x80000000) 325 ; CHECK: [[COPY6:%[0-9]+]]:gprc_and_gprc_nor0 = COPY %32.sub_32 326 ; CHECK: [[ADDI:%[0-9]+]]:gprc_and_gprc_nor0 = ADDI [[COPY6]], -2 327 ; CHECK: [[ADDI1:%[0-9]+]]:gprc = nuw ADDI [[ADDI]], 102 328 ; CHECK: bb.4 (%ir-block.17): 329 ; CHECK: successors: %bb.8(0x40000000), %bb.5(0x40000000) 330 ; CHECK: [[PHI:%[0-9]+]]:g8rc = PHI [[LI8_]], %bb.18, %32, %bb.3 331 ; CHECK: [[PHI1:%[0-9]+]]:gprc = PHI [[LI1]], %bb.18, [[ADDI1]], %bb.3 332 ; CHECK: [[PHI2:%[0-9]+]]:gprc = PHI [[LI]], %bb.18, %27, %bb.3 333 ; CHECK: [[ANDI8_rec:%[0-9]+]]:g8rc = ANDI8_rec [[RLDICL]], 1, implicit-def $cr0 334 ; CHECK: [[COPY7:%[0-9]+]]:crbitrc = COPY $cr0gt 335 ; CHECK: BCn killed [[COPY7]], %bb.8 336 ; CHECK: B %bb.5 337 ; CHECK: bb.5 (%ir-block.23): 338 ; CHECK: successors: %bb.7(0x2aaaaaab), %bb.6(0x55555555) 339 ; CHECK: [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[PHI]], 2, 61 340 ; CHECK: [[LWZX:%[0-9]+]]:gprc = LWZX [[COPY2]], [[RLDICR]] :: (load 4 from %ir.24, !tbaa !2) 341 ; CHECK: [[ADD4_:%[0-9]+]]:gprc = nsw ADD4 killed [[LWZX]], [[PHI2]] 342 ; CHECK: BCC 76, [[CMPLWI1]], %bb.7 343 ; CHECK: B %bb.6 344 ; CHECK: bb.6 (%ir-block.23): 345 ; CHECK: successors: %bb.7(0x80000000) 346 ; CHECK: [[CMPLWI3:%[0-9]+]]:crrc = CMPLWI [[COPY5]], 1 347 ; CHECK: [[COPY8:%[0-9]+]]:gprc = COPY [[PHI]].sub_32 348 ; CHECK: [[LIS1:%[0-9]+]]:gprc = LIS 34952 349 ; CHECK: [[ORI1:%[0-9]+]]:gprc = ORI killed [[LIS1]], 34953 350 ; CHECK: [[MULHWU:%[0-9]+]]:gprc = MULHWU [[COPY8]], killed [[ORI1]] 351 ; CHECK: [[RLWINM:%[0-9]+]]:gprc = RLWINM [[MULHWU]], 28, 4, 31 352 ; CHECK: [[MULLI:%[0-9]+]]:gprc = MULLI killed [[RLWINM]], 30 353 ; CHECK: [[SUBF:%[0-9]+]]:gprc = SUBF killed [[MULLI]], [[COPY8]] 354 ; CHECK: [[COPY9:%[0-9]+]]:gprc = COPY [[PHI]].sub_32 355 ; CHECK: [[RLWINM1:%[0-9]+]]:gprc_and_gprc_nor0 = RLWINM [[COPY9]], 1, 0, 30 356 ; CHECK: [[ISEL:%[0-9]+]]:gprc = ISEL [[RLWINM1]], [[SUBF]], [[CMPLWI3]].sub_eq 357 ; CHECK: B %bb.7 358 ; CHECK: bb.7 (%ir-block.33): 359 ; CHECK: successors: %bb.8(0x80000000) 360 ; CHECK: [[PHI3:%[0-9]+]]:gprc = PHI [[PHI1]], %bb.5, [[ISEL]], %bb.6 361 ; CHECK: [[ADD4_1:%[0-9]+]]:gprc = nsw ADD4 [[PHI3]], [[ADD4_]] 362 ; CHECK: STWX killed [[ADD4_1]], [[COPY1]], [[RLDICR]] :: (store 4 into %ir.36, !tbaa !2) 363 ; CHECK: bb.8 (%ir-block.37): 364 ; CHECK: [[LI8_2:%[0-9]+]]:g8rc = LI8 0 365 ; CHECK: $x3 = COPY [[LI8_2]] 366 ; CHECK: BLR8 implicit $lr8, implicit $rm, implicit $x3 367 ; CHECK: bb.9 (%ir-block.38): 368 ; CHECK: successors: %bb.11(0x2aaaaaab), %bb.10(0x55555555) 369 ; CHECK: [[PHI4:%[0-9]+]]:g8rc_and_g8rc_nox0 = PHI [[LI8_1]], %bb.2, %32, %bb.17 370 ; CHECK: [[PHI5:%[0-9]+]]:gprc = PHI [[LI2]], %bb.2, %27, %bb.17 371 ; CHECK: [[PHI6:%[0-9]+]]:g8rc_and_g8rc_nox0 = PHI [[ADDI8_]], %bb.2, %55, %bb.17 372 ; CHECK: [[PHI7:%[0-9]+]]:g8rc_and_g8rc_nox0 = PHI [[ADDI8_1]], %bb.2, %15, %bb.17 373 ; CHECK: [[COPY10:%[0-9]+]]:gprc_and_gprc_nor0 = COPY [[PHI4]].sub_32 374 ; CHECK: [[MULHWU1:%[0-9]+]]:gprc = MULHWU [[COPY10]], [[ORI]] 375 ; CHECK: [[RLWINM2:%[0-9]+]]:gprc = RLWINM [[MULHWU1]], 28, 4, 31 376 ; CHECK: [[MULLI1:%[0-9]+]]:gprc = nsw MULLI killed [[RLWINM2]], -30 377 ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF1]], killed [[MULLI1]], %subreg.sub_32 378 ; CHECK: [[RLDICL2:%[0-9]+]]:g8rc = RLDICL killed [[INSERT_SUBREG1]], 0, 32 379 ; CHECK: BCC 76, [[CMPLWI1]], %bb.11 380 ; CHECK: B %bb.10 381 ; CHECK: bb.10 (%ir-block.38): 382 ; CHECK: successors: %bb.12(0x80000000) 383 ; CHECK: [[ADD8_:%[0-9]+]]:g8rc = ADD8 [[PHI4]], [[RLDICL2]] 384 ; CHECK: [[COPY11:%[0-9]+]]:gprc = COPY [[ADD8_]].sub_32 385 ; CHECK: [[COPY12:%[0-9]+]]:gprc = COPY [[PHI4]].sub_32 386 ; CHECK: [[RLWINM3:%[0-9]+]]:gprc_and_gprc_nor0 = RLWINM [[COPY12]], 1, 0, 30 387 ; CHECK: [[ISEL1:%[0-9]+]]:gprc = ISEL [[RLWINM3]], [[COPY11]], [[CMPLWI2]].sub_eq 388 ; CHECK: B %bb.12 389 ; CHECK: bb.11 (%ir-block.56): 390 ; CHECK: successors: %bb.12(0x80000000) 391 ; CHECK: [[ADDI2:%[0-9]+]]:gprc = nuw nsw ADDI [[COPY10]], 100 392 ; CHECK: B %bb.12 393 ; CHECK: bb.12 (%ir-block.60): 394 ; CHECK: successors: %bb.15(0x2aaaaaab), %bb.13(0x55555555) 395 ; CHECK: [[PHI8:%[0-9]+]]:gprc = PHI [[ADDI2]], %bb.11, [[ISEL1]], %bb.10 396 ; CHECK: [[ADDI8_4:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[PHI7]], 8 397 ; CHECK: [[LWZU:%[0-9]+]]:gprc, [[LWZU1:%[0-9]+]]:g8rc_and_g8rc_nox0 = LWZU 8, [[PHI6]] :: (load 4 from %ir.46, !tbaa !2) 398 ; CHECK: [[ADD4_2:%[0-9]+]]:gprc = nsw ADD4 [[LWZU]], [[PHI5]] 399 ; CHECK: [[ADD4_3:%[0-9]+]]:gprc = nsw ADD4 [[PHI8]], [[ADD4_2]] 400 ; CHECK: STW killed [[ADD4_3]], 0, [[ADDI8_4]] :: (store 4 into %ir.44, !tbaa !2) 401 ; CHECK: [[LWZ:%[0-9]+]]:gprc = LWZ 4, [[LWZU1]] :: (load 4 from %ir.uglygep1112.cast, !tbaa !2) 402 ; CHECK: BCC 76, [[CMPLWI2]], %bb.15 403 ; CHECK: B %bb.13 404 ; CHECK: bb.13 (%ir-block.60): 405 ; CHECK: successors: %bb.14(0x40000001), %bb.16(0x3fffffff) 406 ; CHECK: BCC 68, [[CMPLWI1]], %bb.16 407 ; CHECK: B %bb.14 408 ; CHECK: bb.14 (%ir-block.67): 409 ; CHECK: successors: %bb.17(0x80000000) 410 ; CHECK: [[ADDI3:%[0-9]+]]:gprc = nuw nsw ADDI [[COPY10]], 101 411 ; CHECK: B %bb.17 412 ; CHECK: bb.15 (%ir-block.69): 413 ; CHECK: successors: %bb.17(0x80000000) 414 ; CHECK: [[ORI8_:%[0-9]+]]:g8rc = ORI8 [[PHI4]], 1 415 ; CHECK: [[COPY13:%[0-9]+]]:gprc = COPY [[ORI8_]].sub_32 416 ; CHECK: [[RLWINM4:%[0-9]+]]:gprc = RLWINM [[COPY13]], 1, 0, 30 417 ; CHECK: B %bb.17 418 ; CHECK: bb.16 (%ir-block.72): 419 ; CHECK: successors: %bb.17(0x80000000) 420 ; CHECK: [[ORI8_1:%[0-9]+]]:g8rc = ORI8 [[RLDICL2]], 1 421 ; CHECK: [[ADD8_1:%[0-9]+]]:g8rc = ADD8 [[PHI4]], [[ORI8_1]] 422 ; CHECK: [[COPY14:%[0-9]+]]:gprc = COPY [[ADD8_1]].sub_32 423 ; CHECK: bb.17 (%ir-block.74): 424 ; CHECK: successors: %bb.9(0x7c000000), %bb.3(0x04000000) 425 ; CHECK: [[PHI9:%[0-9]+]]:gprc = PHI [[ADDI3]], %bb.14, [[RLWINM4]], %bb.15, [[COPY14]], %bb.16 426 ; CHECK: [[COPY15:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY [[ADDI8_4]] 427 ; CHECK: [[ADD4_4:%[0-9]+]]:gprc = nsw ADD4 [[LWZ]], [[ADD4_2]] 428 ; CHECK: [[ADD4_5:%[0-9]+]]:gprc = nsw ADD4 [[PHI9]], [[ADD4_4]] 429 ; CHECK: STW killed [[ADD4_5]], 4, [[COPY15]] :: (store 4 into %ir.uglygep78.cast, !tbaa !2) 430 ; CHECK: [[ADDI8_5:%[0-9]+]]:g8rc = nuw nsw ADDI8 [[PHI4]], 2 431 ; CHECK: BDNZ8 %bb.9, implicit-def dead $ctr8, implicit $ctr8 432 ; CHECK: B %bb.3 433 bb.0 (%ir-block.5): 434 successors: %bb.1(0x50000000), %bb.9(0x30000000) 435 liveins: $x3, $x5, $x6, $x7 436 437 %38:g8rc = COPY $x7 438 %37:g8rc_and_g8rc_nox0 = COPY $x6 439 %36:g8rc_and_g8rc_nox0 = COPY $x5 440 %34:g8rc = COPY $x3 441 %39:gprc = COPY %34.sub_32 442 %40:gprc = COPY %38.sub_32 443 %41:crrc = CMPWI %40, 1 444 BCC 12, killed %41, %bb.9 445 B %bb.1 446 447 bb.1 (%ir-block.7): 448 %46:g8rc = IMPLICIT_DEF 449 %45:g8rc = INSERT_SUBREG %46, %40, %subreg.sub_32 450 %0:g8rc = RLDICL killed %45, 0, 32 451 %44:gprc = LI 0 452 %43:gprc = LI 100 453 %42:g8rc = LI8 0 454 %47:crrc = CMPLWI %40, 1 455 %95:crrc = CMPLWI %39, 3 456 BCC 76, killed %47, %bb.4 457 B %bb.2 458 459 bb.2 (%ir-block.10): 460 %50:g8rc_and_g8rc_nox0 = RLWINM8 %0, 0, 0, 30 461 %1:g8rc = ADDI8 %36, -8 462 %2:g8rc = ADDI8 %37, -8 463 %51:g8rc = nsw ADDI8 killed %50, -2 464 %52:g8rc_and_g8rc_nox0 = RLDICL %51, 63, 1 465 %53:g8rc = nuw ADDI8 killed %52, 1 466 MTCTR8loop killed %53, implicit-def dead $ctr8 467 %49:gprc = LI 0 468 %48:g8rc = LI8 0 469 %56:gprc = LIS 34952 470 %57:gprc = ORI %56, 34953 471 %62:g8rc = IMPLICIT_DEF 472 %69:crrc = CMPLWI %39, 1 473 B %bb.10 474 475 bb.3 (%ir-block.15): 476 %3:gprc = nuw ADDI %33, 102 477 478 bb.4 (%ir-block.17): 479 %4:g8rc = PHI %42, %bb.1, %32, %bb.3 480 %5:gprc = PHI %43, %bb.1, %3, %bb.3 481 %6:gprc = PHI %44, %bb.1, %27, %bb.3 482 %90:g8rc = ANDI8_rec %0, 1, implicit-def $cr0 483 %75:crbitrc = COPY $cr0gt 484 BCn killed %75, %bb.9 485 B %bb.5 486 487 bb.5 (%ir-block.23): 488 successors: %bb.8(0x2aaaaaab), %bb.21(0x55555555) 489 490 %76:g8rc = RLDICR %4, 2, 61 491 %77:gprc = LWZX %36, %76 :: (load 4 from %ir.24, !tbaa !2) 492 %7:gprc = nsw ADD4 killed %77, %6 493 BCC 76, %95, %bb.8 494 B %bb.21 495 496 bb.21 (%ir-block.23): 497 %79:crrc = CMPLWI %39, 1 498 %81:gprc = COPY %4.sub_32 499 %82:gprc = LIS 34952 500 %83:gprc = ORI killed %82, 34953 501 %84:gprc = MULHWU %81, killed %83 502 %85:gprc = RLWINM %84, 28, 4, 31 503 %86:gprc = MULLI killed %85, 30 504 %9:gprc = SUBF killed %86, %81 505 %80:gprc = COPY %4.sub_32 506 %8:gprc_and_gprc_nor0 = RLWINM %80, 1, 0, 30 507 %91:gprc = ISEL %8, %9, %79.sub_eq 508 B %bb.8 509 510 bb.8 (%ir-block.33): 511 %10:gprc = PHI %5, %bb.5, %91, %bb.21 512 %87:gprc = nsw ADD4 %10, %7 513 STWX killed %87, %37, %76 :: (store 4 into %ir.36, !tbaa !2) 514 515 bb.9 (%ir-block.37): 516 %89:g8rc = LI8 0 517 $x3 = COPY %89 518 BLR8 implicit $lr8, implicit $rm, implicit $x3 519 520 bb.10 (%ir-block.38): 521 successors: %bb.12(0x2aaaaaab), %bb.19(0x55555555) 522 523 %11:g8rc_and_g8rc_nox0 = PHI %48, %bb.2, %32, %bb.18 524 %12:gprc = PHI %49, %bb.2, %27, %bb.18 525 %13:g8rc_and_g8rc_nox0 = PHI %1, %bb.2, %17, %bb.18 526 %14:g8rc_and_g8rc_nox0 = PHI %2, %bb.2, %15, %bb.18 527 %16:g8rc_and_g8rc_nox0 = ADDI8 %14, 8 528 %15:g8rc_and_g8rc_nox0 = COPY %16 529 %54:gprc, %55:g8rc_and_g8rc_nox0 = LWZU 8, %13 :: (load 4 from %ir.46, !tbaa !2) 530 %17:g8rc_and_g8rc_nox0 = COPY %55 531 %18:gprc_and_gprc_nor0 = COPY %11.sub_32 532 %58:gprc = MULHWU %18, %57 533 %59:gprc = RLWINM %58, 28, 4, 31 534 %60:gprc = nsw MULLI killed %59, -30 535 %61:g8rc = INSERT_SUBREG %62, killed %60, %subreg.sub_32 536 %19:g8rc = RLDICL killed %61, 0, 32 537 %20:g8rc = ORI8 %19, 1 538 %21:gprc = nsw ADD4 killed %54, %12 539 BCC 76, %95, %bb.12 540 B %bb.19 541 542 bb.19 (%ir-block.38): 543 %66:g8rc = ADD8 %11, %19 544 %24:gprc = COPY %66.sub_32 545 %65:gprc = COPY %11.sub_32 546 %22:gprc_and_gprc_nor0 = RLWINM %65, 1, 0, 30 547 %93:gprc = ISEL %22, %24, %69.sub_eq 548 B %bb.14 549 550 bb.12 (%ir-block.56): 551 %23:gprc = nuw nsw ADDI %18, 100 552 B %bb.14 553 554 bb.14 (%ir-block.60): 555 successors: %bb.16(0x2aaaaaab), %bb.20(0x55555555) 556 557 %25:gprc = PHI %23, %bb.12, %93, %bb.19 558 %67:gprc = nsw ADD4 %25, %21 559 STW killed %67, 0, %16 :: (store 4 into %ir.44, !tbaa !2) 560 %26:g8rc = ORI8 %11, 1 561 %68:gprc = LWZ 4, %17 :: (load 4 from %ir.uglygep1112.cast, !tbaa !2) 562 %27:gprc = nsw ADD4 killed %68, %21 563 BCC 76, %69, %bb.16 564 B %bb.20 565 566 bb.20 (%ir-block.60): 567 successors: %bb.15(0x40000001), %bb.17(0x3fffffff) 568 569 BCC 68, %95, %bb.17 570 B %bb.15 571 572 bb.15 (%ir-block.67): 573 %28:gprc = nuw nsw ADDI %18, 101 574 B %bb.18 575 576 bb.16 (%ir-block.69): 577 %71:gprc = COPY %26.sub_32 578 %29:gprc = RLWINM %71, 1, 0, 30 579 B %bb.18 580 581 bb.17 (%ir-block.72): 582 %72:g8rc = ADD8 %11, %20 583 %30:gprc = COPY %72.sub_32 584 585 bb.18 (%ir-block.74): 586 successors: %bb.10(0x7c000000), %bb.3(0x04000000) 587 588 %31:gprc = PHI %28, %bb.15, %29, %bb.16, %30, %bb.17 589 %73:gprc = nsw ADD4 %31, %27 590 STW killed %73, 4, %15 :: (store 4 into %ir.uglygep78.cast, !tbaa !2) 591 %32:g8rc = nuw nsw ADDI8 %11, 2 592 %74:gprc_and_gprc_nor0 = COPY %32.sub_32 593 %33:gprc_and_gprc_nor0 = ADDI killed %74, -2 594 BDNZ8 %bb.10, implicit-def dead $ctr8, implicit $ctr8 595 B %bb.3 596 597... 598