Home
last modified time | relevance | path

Searched refs:OpRC (Results 1 – 17 of 17) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DBreakFalseDeps.cpp125 const TargetRegisterClass *OpRC = in pickBestRegisterForUndef() local
132 !OpRC->contains(CurrMO.getReg())) in pickBestRegisterForUndef()
144 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef()
DMachineInstr.cpp902 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI); in getRegClassConstraintEffect() local
908 if (OpRC) in getRegClassConstraintEffect()
909 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx); in getRegClassConstraintEffect()
912 } else if (OpRC) in getRegClassConstraintEffect()
913 CurRC = TRI->getCommonSubClass(CurRC, OpRC); in getRegClassConstraintEffect()
/external/llvm-project/llvm/lib/CodeGen/
DBreakFalseDeps.cpp134 const TargetRegisterClass *OpRC = in pickBestRegisterForUndef() local
141 !OpRC->contains(CurrMO.getReg())) in pickBestRegisterForUndef()
153 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef()
DMachineInstr.cpp946 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI); in getRegClassConstraintEffect() local
952 if (OpRC) in getRegClassConstraintEffect()
953 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx); in getRegClassConstraintEffect()
956 } else if (OpRC) in getRegClassConstraintEffect()
957 CurRC = TRI->getCommonSubClass(CurRC, OpRC); in getRegClassConstraintEffect()
DRegAllocFast.cpp1029 const TargetRegisterClass *OpRC = MRI->getRegClass(Reg); in addRegClassDefCounts() local
1034 if (OpRC->hasSubClassEq(IdxRC)) in addRegClassDefCounts()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp312 const TargetRegisterClass *OpRC = nullptr; in AddRegisterOperand() local
314 OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF); in AddRegisterOperand()
316 if (OpRC) { in AddRegisterOperand()
318 = MRI->constrainRegClass(VReg, OpRC, MinRCSize); in AddRegisterOperand()
320 OpRC = TRI->getAllocatableClass(OpRC); in AddRegisterOperand()
321 assert(OpRC && "Constraints cannot be fulfilled for allocation"); in AddRegisterOperand()
322 Register NewVReg = MRI->createVirtualRegister(OpRC); in AddRegisterOperand()
381 const TargetRegisterClass *OpRC = in AddOperand() local
388 if (OpRC && IIRC && OpRC != IIRC && Register::isVirtualRegister(VReg)) { in AddOperand()
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp320 const TargetRegisterClass *OpRC = nullptr; in AddRegisterOperand() local
322 OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF); in AddRegisterOperand()
324 if (OpRC) { in AddRegisterOperand()
326 = MRI->constrainRegClass(VReg, OpRC, MinRCSize); in AddRegisterOperand()
328 OpRC = TRI->getAllocatableClass(OpRC); in AddRegisterOperand()
329 assert(OpRC && "Constraints cannot be fulfilled for allocation"); in AddRegisterOperand()
330 Register NewVReg = MRI->createVirtualRegister(OpRC); in AddRegisterOperand()
389 const TargetRegisterClass *OpRC = in AddOperand() local
396 if (OpRC && IIRC && OpRC != IIRC && Register::isVirtualRegister(VReg)) { in AddOperand()
/external/llvm-project/llvm/lib/Target/X86/
DX86SpeculativeLoadHardening.cpp1662 auto *OpRC = MRI->getRegClass(OpReg); in hardenLoadAddr() local
1663 Register TmpReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr()
1667 if (!Subtarget->hasVLX() && (OpRC->hasSuperClassEq(&X86::VR128RegClass) || in hardenLoadAddr()
1668 OpRC->hasSuperClassEq(&X86::VR256RegClass))) { in hardenLoadAddr()
1670 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128RegClass); in hardenLoadAddr()
1684 Register VBStateReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr()
1704 } else if (OpRC->hasSuperClassEq(&X86::VR128XRegClass) || in hardenLoadAddr()
1705 OpRC->hasSuperClassEq(&X86::VR256XRegClass) || in hardenLoadAddr()
1706 OpRC->hasSuperClassEq(&X86::VR512RegClass)) { in hardenLoadAddr()
1708 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128XRegClass); in hardenLoadAddr()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86SpeculativeLoadHardening.cpp2035 auto *OpRC = MRI->getRegClass(OpReg); in hardenLoadAddr() local
2036 Register TmpReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr()
2040 if (!Subtarget->hasVLX() && (OpRC->hasSuperClassEq(&X86::VR128RegClass) || in hardenLoadAddr()
2041 OpRC->hasSuperClassEq(&X86::VR256RegClass))) { in hardenLoadAddr()
2043 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128RegClass); in hardenLoadAddr()
2057 Register VBStateReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr()
2077 } else if (OpRC->hasSuperClassEq(&X86::VR128XRegClass) || in hardenLoadAddr()
2078 OpRC->hasSuperClassEq(&X86::VR256XRegClass) || in hardenLoadAddr()
2079 OpRC->hasSuperClassEq(&X86::VR512RegClass)) { in hardenLoadAddr()
2081 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128XRegClass); in hardenLoadAddr()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp794 const TargetRegisterClass *OpRC = in processPHINode() local
796 if (!TRI->isSGPRClass(OpRC) && OpRC != &AMDGPU::VS_32RegClass && in processPHINode()
797 OpRC != &AMDGPU::VS_64RegClass) { in processPHINode()
DSIInstrInfo.cpp4290 const TargetRegisterClass *OpRC = RI.getSubClassWithSubReg( in legalizeGenericOperand() local
4294 if (DstRC == OpRC) in legalizeGenericOperand()
4554 const TargetRegisterClass *OpRC = in legalizeOperands() local
4556 if (RI.hasVectorRegisters(OpRC)) { in legalizeOperands()
4557 VRC = OpRC; in legalizeOperands()
4559 SRC = OpRC; in legalizeOperands()
4616 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg()); in legalizeOperands() local
4617 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC); in legalizeOperands()
4618 if (VRC == OpRC) in legalizeOperands()
5823 const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass); in findUsedSGPR() local
[all …]
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp834 const TargetRegisterClass *OpRC = in processPHINode() local
836 if (!TRI->isSGPRClass(OpRC) && OpRC != &AMDGPU::VS_32RegClass && in processPHINode()
837 OpRC != &AMDGPU::VS_64RegClass) { in processPHINode()
DSIInstrInfo.cpp4795 const TargetRegisterClass *OpRC = RI.getSubClassWithSubReg( in legalizeGenericOperand() local
4799 if (DstRC == OpRC) in legalizeGenericOperand()
5104 const TargetRegisterClass *OpRC = in legalizeOperands() local
5106 if (RI.hasVectorRegisters(OpRC)) { in legalizeOperands()
5107 VRC = OpRC; in legalizeOperands()
5109 SRC = OpRC; in legalizeOperands()
5166 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg()); in legalizeOperands() local
5167 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC); in legalizeOperands()
5168 if (VRC == OpRC) in legalizeOperands()
6595 const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass); in findUsedSGPR() local
[all …]
/external/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp2236 const TargetRegisterClass *OpRC = in legalizeOperands() local
2238 if (RI.hasVGPRs(OpRC)) { in legalizeOperands()
2239 VRC = OpRC; in legalizeOperands()
2241 SRC = OpRC; in legalizeOperands()
2290 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg()); in legalizeOperands() local
2291 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC); in legalizeOperands()
2292 if (VRC == OpRC) in legalizeOperands()
3003 const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass); in findUsedSGPR() local
3004 bool IsRequiredSGPR = RI.isSGPRClass(OpRC); in findUsedSGPR()
/external/llvm/lib/CodeGen/
DMachineInstr.cpp1246 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI); in getRegClassConstraintEffect() local
1252 if (OpRC) in getRegClassConstraintEffect()
1253 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx); in getRegClassConstraintEffect()
1256 } else if (OpRC) in getRegClassConstraintEffect()
1257 CurRC = TRI->getCommonSubClass(CurRC, OpRC); in getRegClassConstraintEffect()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonBitSimplify.cpp1876 auto *OpRC = HII.getRegClass(HII.get(Opc), OpNum, &HRI, MF); in validateReg() local
1878 return OpRC->hasSubClassEq(RRC); in validateReg()
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonBitSimplify.cpp1886 auto *OpRC = HII.getRegClass(HII.get(Opc), OpNum, &HRI, MF); in validateReg() local
1888 return OpRC->hasSubClassEq(RRC); in validateReg()