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Searched refs:OpSize32 (Results 1 – 25 of 43) sorted by relevance

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/external/llvm/lib/Target/X86/
DX86InstrExtension.td20 "{cwtl|cwde}", [], IIC_CBW>, OpSize32; // EAX = signext(AX)
27 "{cltd|cdq}", [], IIC_CBW>, OpSize32; // EDX:EAX = signext(EAX)
54 OpSize32, Sched<[WriteALU]>;
58 OpSize32, Sched<[WriteALULd]>;
62 OpSize32, Sched<[WriteALU]>;
66 OpSize32, TB, Sched<[WriteALULd]>;
80 OpSize32, Sched<[WriteALU]>;
84 OpSize32, Sched<[WriteALULd]>;
88 OpSize32, Sched<[WriteALU]>;
92 TB, OpSize32, Sched<[WriteALULd]>;
[all …]
DX86InstrSystem.td82 "in{l}\t{%dx, %eax|eax, dx}", [], IIC_IN_RR>, OpSize32;
92 "in{l}\t{$port, %eax|eax, $port}", [], IIC_IN_RI>, OpSize32;
102 "out{l}\t{%eax, %dx|dx, eax}", [], IIC_OUT_RR>, OpSize32;
112 "out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>, OpSize32;
173 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize32;
180 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize32;
187 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize32;
194 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize32;
215 OpSize32;
218 OpSize32;
[all …]
DX86InstrControl.td25 "ret{l}", [], IIC_RET>, OpSize32,
28 "ret{q}", [], IIC_RET>, OpSize32,
35 [], IIC_RET_IMM>, OpSize32,
39 [], IIC_RET_IMM>, OpSize32,
45 "{l}ret{l|f}", [], IIC_RET>, OpSize32;
51 "{l}ret{l|f}\t$amt", [], IIC_RET>, OpSize32;
63 IIC_IRET>, OpSize32;
79 "jmp\t$dst", [], IIC_JMP_REL>, OpSize32;
92 [], IIC_Jcc>, TB, OpSize32;
144 OpSize32, Sched<[WriteJump]>;
[all …]
DX86InstrShiftRotate.td28 [(set GR32:$dst, (shl GR32:$src1, CL))], IIC_SR>, OpSize32;
46 OpSize32;
62 "shl{l}\t$dst", [], IIC_SR>, OpSize32;
83 OpSize32;
99 IIC_SR>, OpSize32;
117 IIC_SR>, OpSize32;
134 [(set GR32:$dst, (srl GR32:$src1, CL))], IIC_SR>, OpSize32;
150 IIC_SR>, OpSize32;
164 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))], IIC_SR>, OpSize32;
183 OpSize32;
[all …]
DX86InstrInfo.td1064 "nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32;
1097 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
1103 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
1105 IIC_POP_MEM>, OpSize32, Requires<[Not64BitMode]>;
1112 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
1116 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
1124 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1127 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1135 IIC_PUSH_MEM>, OpSize32, Requires<[Not64BitMode]>;
1171 OpSize32, Requires<[Not64BitMode]>;
[all …]
DX86InstrArithmetic.td27 OpSize32, Requires<[Not64BitMode]>;
33 OpSize32, Requires<[In64BitMode]>;
77 IIC_MUL32_REG>, OpSize32, Sched<[WriteIMul]>;
103 [], IIC_MUL32_MEM>, OpSize32, SchedLoadReg<WriteIMulLd>;
122 IIC_IMUL32_RR>, OpSize32, Sched<[WriteIMul]>;
141 "imul{l}\t$src", [], IIC_IMUL32_MEM>, OpSize32,
166 TB, OpSize32;
190 TB, OpSize32;
224 IIC_IMUL32_RRI>, OpSize32;
230 IIC_IMUL32_RRI>, OpSize32;
[all …]
DX86InstrTSX.td30 "xbegin\t$dst", []>, OpSize32, Requires<[HasRTM]>;
DX86InstrCMovSetCC.td31 IIC_CMOV32_RR>, TB, OpSize32;
53 TB, OpSize32;
/external/llvm-project/llvm/lib/Target/X86/
DX86InstrExtension.td19 "{cwtl|cwde}", []>, OpSize32, Sched<[WriteALU]>;
31 "{cltd|cdq}", []>, OpSize32, Sched<[WriteALU]>;
50 OpSize32, Sched<[WriteALU]>;
54 OpSize32, Sched<[WriteALULd]>;
58 OpSize32, Sched<[WriteALU]>;
62 OpSize32, TB, Sched<[WriteALULd]>;
76 OpSize32, Sched<[WriteALU]>;
80 OpSize32, Sched<[WriteALULd]>;
84 OpSize32, Sched<[WriteALU]>;
88 TB, OpSize32, Sched<[WriteALULd]>;
[all …]
DX86InstrControl.td24 "ret{l}", []>, OpSize32, Requires<[Not64BitMode]>;
26 "ret{q}", []>, OpSize32, Requires<[In64BitMode]>;
30 "ret{l}\t$amt", []>, OpSize32, Requires<[Not64BitMode]>;
32 "ret{q}\t$amt", []>, OpSize32, Requires<[In64BitMode]>;
36 "{l}ret{l|f}", []>, OpSize32;
42 "{l}ret{l|f}\t$amt", []>, OpSize32;
53 def IRET32 : I <0xcf, RawFrm, (outs), (ins), "iret{l|d}", []>, OpSize32;
68 "jmp\t$dst", []>, OpSize32;
87 []>, TB, OpSize32;
136 OpSize32, Sched<[WriteJump]>;
[all …]
DX86InstrSystem.td30 "ud1{l} {$src2, $src1|$src1, $src2}", []>, TB, OpSize32;
37 "ud1{l} {$src2, $src1|$src1, $src2}", []>, TB, OpSize32;
91 OpSize32;
101 "in{l}\t{$port, %eax|eax, $port}", []>, OpSize32;
110 OpSize32;
120 "out{l}\t{%eax, $port|$port, eax}", []>, OpSize32;
182 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;
192 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;
218 OpSize32, NotMemoryFoldable;
221 OpSize32, NotMemoryFoldable;
[all …]
DX86InstrShiftRotate.td27 [(set GR32:$dst, (shl GR32:$src1, CL))]>, OpSize32;
45 OpSize32;
60 "shl{l}\t$dst", []>, OpSize32;
79 OpSize32;
97 OpSize32;
114 OpSize32;
131 [(set GR32:$dst, (srl GR32:$src1, CL))]>, OpSize32;
147 OpSize32;
161 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>, OpSize32;
179 OpSize32;
[all …]
DX86InstrInfo.td1266 "nop{l}\t$zero", []>, TB, OpSize32, NotMemoryFoldable;
1274 "nop{l}\t$zero", []>, TB, OpSize32, NotMemoryFoldable;
1309 OpSize32, Requires<[Not64BitMode]>;
1315 OpSize32, Requires<[Not64BitMode]>, NotMemoryFoldable;
1322 OpSize32, Requires<[Not64BitMode]>;
1329 OpSize32, Requires<[Not64BitMode]>;
1335 OpSize32, Requires<[Not64BitMode]>, NotMemoryFoldable;
1344 "push{l}\t$imm", []>, OpSize32,
1347 "push{l}\t$imm", []>, OpSize32,
1355 OpSize32, Requires<[Not64BitMode]>;
[all …]
DX86InstrArithmetic.td26 OpSize32, Requires<[Not64BitMode]>;
32 OpSize32, Requires<[In64BitMode]>;
76 OpSize32, Sched<[WriteIMul32]>;
100 "mul{l}\t$src", []>, OpSize32, SchedLoadReg<WriteIMul32>;
120 OpSize32, Sched<[WriteIMul32]>;
138 "imul{l}\t$src", []>, OpSize32, SchedLoadReg<WriteIMul32>;
163 Sched<[WriteIMul32Reg]>, TB, OpSize32;
184 Sched<[WriteIMul32Reg.Folded, WriteIMul32Reg.ReadAfterFold]>, TB, OpSize32;
218 Sched<[WriteIMul32Imm]>, OpSize32;
224 Sched<[WriteIMul32Imm]>, OpSize32;
[all …]
DX86InstrTSX.td31 "xbegin\t$dst", []>, OpSize32;
DX86InstrCMovSetCC.td30 TB, OpSize32;
49 timm:$cond, EFLAGS))]>, TB, OpSize32;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrExtension.td19 "{cwtl|cwde}", []>, OpSize32, Sched<[WriteALU]>;
31 "{cltd|cdq}", []>, OpSize32, Sched<[WriteALU]>;
50 OpSize32, Sched<[WriteALU]>;
54 OpSize32, Sched<[WriteALULd]>;
58 OpSize32, Sched<[WriteALU]>;
62 OpSize32, TB, Sched<[WriteALULd]>;
76 OpSize32, Sched<[WriteALU]>;
80 OpSize32, Sched<[WriteALULd]>;
84 OpSize32, Sched<[WriteALU]>;
88 TB, OpSize32, Sched<[WriteALULd]>;
[all …]
DX86InstrControl.td24 "ret{l}", []>, OpSize32, Requires<[Not64BitMode]>;
26 "ret{q}", []>, OpSize32, Requires<[In64BitMode]>;
30 "ret{l}\t$amt", []>, OpSize32, Requires<[Not64BitMode]>;
32 "ret{q}\t$amt", []>, OpSize32, Requires<[In64BitMode]>;
36 "{l}ret{l|f}", []>, OpSize32;
42 "{l}ret{l|f}\t$amt", []>, OpSize32;
53 def IRET32 : I <0xcf, RawFrm, (outs), (ins), "iret{l|d}", []>, OpSize32;
68 "jmp\t$dst", []>, OpSize32;
87 []>, TB, OpSize32;
136 OpSize32, Sched<[WriteJump]>;
[all …]
DX86InstrSystem.td77 OpSize32;
87 "in{l}\t{$port, %eax|eax, $port}", []>, OpSize32;
96 OpSize32;
106 "out{l}\t{%eax, $port|$port, eax}", []>, OpSize32;
168 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;
178 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;
205 OpSize32, NotMemoryFoldable;
208 OpSize32, NotMemoryFoldable;
228 OpSize32, NotMemoryFoldable;
231 OpSize32, NotMemoryFoldable;
[all …]
DX86InstrShiftRotate.td27 [(set GR32:$dst, (shl GR32:$src1, CL))]>, OpSize32;
45 OpSize32;
60 "shl{l}\t$dst", []>, OpSize32;
79 OpSize32;
97 OpSize32;
114 OpSize32;
131 [(set GR32:$dst, (srl GR32:$src1, CL))]>, OpSize32;
147 OpSize32;
161 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>, OpSize32;
179 OpSize32;
[all …]
DX86InstrInfo.td1211 "nop{l}\t$zero", []>, TB, OpSize32, NotMemoryFoldable;
1219 "nop{l}\t$zero", []>, TB, OpSize32, NotMemoryFoldable;
1254 OpSize32, Requires<[Not64BitMode]>;
1260 OpSize32, Requires<[Not64BitMode]>, NotMemoryFoldable;
1267 OpSize32, Requires<[Not64BitMode]>;
1274 OpSize32, Requires<[Not64BitMode]>;
1280 OpSize32, Requires<[Not64BitMode]>, NotMemoryFoldable;
1289 "push{l}\t$imm", []>, OpSize32,
1292 "push{l}\t$imm", []>, OpSize32,
1300 OpSize32, Requires<[Not64BitMode]>;
[all …]
DX86InstrArithmetic.td26 OpSize32, Requires<[Not64BitMode]>;
32 OpSize32, Requires<[In64BitMode]>;
76 OpSize32, Sched<[WriteIMul32]>;
100 "mul{l}\t$src", []>, OpSize32, SchedLoadReg<WriteIMul32>;
120 OpSize32, Sched<[WriteIMul32]>;
138 "imul{l}\t$src", []>, OpSize32, SchedLoadReg<WriteIMul32>;
163 Sched<[WriteIMul32Reg]>, TB, OpSize32;
184 Sched<[WriteIMul32Reg.Folded, WriteIMul32Reg.ReadAfterFold]>, TB, OpSize32;
218 Sched<[WriteIMul32Imm]>, OpSize32;
224 Sched<[WriteIMul32Imm]>, OpSize32;
[all …]
DX86InstrTSX.td31 "xbegin\t$dst", []>, OpSize32;
DX86InstrCMovSetCC.td30 TB, OpSize32;
49 timm:$cond, EFLAGS))]>, TB, OpSize32;
/external/llvm-project/llvm/utils/TableGen/
DX86RecognizableInstr.h145 OpSize16 = 1, OpSize32 = 2 enumerator

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