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Searched refs:PSTATE (Results 1 – 18 of 18) sorted by relevance

/external/arm-trusted-firmware/drivers/imx/usdhc/
Dimx_usdhc.c124 state = mmio_read_32(reg_base + PSTATE); in imx_usdhc_send_cmd()
127 while (mmio_read_32(reg_base + PSTATE) & PSTATE_DLA) in imx_usdhc_send_cmd()
Dimx_usdhc.h41 #define PSTATE 0x024 macro
/external/arm-trusted-firmware/docs/design/
Dinterrupt-framework-design.rst214 #. Interrupt exceptions (``PSTATE.I`` and ``F`` bits) are masked during execution
453 masks all interrupts (``PSTATE.DAIF`` bits) when it calls
530 #. **CSS=0, TEL3=0**. If ``PSTATE.F=0``, Secure-EL1 interrupts will be
534 If ``PSTATE.F=1`` then Secure-EL1 interrupts will be handled as per the
538 know the state of the system, general purpose and the ``PSTATE`` registers
548 is in secure state. They will not be visible to the SP. The ``PSTATE.F`` bit
557 #. **CSS=0, TEL3=0**. If ``PSTATE.I=0``, non-secure interrupts will be
567 If ``PSTATE.I=1`` then the non-secure interrupt will pend until execution
571 be visible to the SP. The ``PSTATE.I`` bit in Secure-EL1/Secure-EL0 will
626 ``PSTATE.I`` and ``PSTATE.F`` bits set.
[all …]
Dfirmware-design.rst637 PSTATE.EL = 3
638 PSTATE.RW = 1
639 PSTATE.DAIF = 0xf
727 PSTATE.EL = 3
728 PSTATE.RW = 1
729 PSTATE.DAIF = 0xf
757 PSTATE.AIF = 0x7
819 PSTATE.AIF = 0x7
/external/llvm-project/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td116 def PSTATE : SparcCtrlReg<6, "PSTATE">;
377 (add TPC, TNPC, TSTATE, TT, TICK, TBA, PSTATE, TL, PIL, CWP,
/external/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td117 def PSTATE : SparcCtrlReg<6, "PSTATE">;
377 (add TPC, TNPC, TSTATE, TT, TICK, TBA, PSTATE, TL, PIL, CWP,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td116 def PSTATE : SparcCtrlReg<6, "PSTATE">;
377 (add TPC, TNPC, TSTATE, TT, TICK, TBA, PSTATE, TL, PIL, CWP,
/external/capstone/bindings/ocaml/
Dtest_arm64.ml41 | ARM64_OP_PSTATE v -> printf "\t\top[%d]: PSTATE = %u\n" i v;
/external/llvm/lib/Target/Sparc/Disassembler/
DSparcDisassembler.cpp121 SP::TPC, SP::TNPC, SP::TSTATE, SP::TT, SP::TICK, SP::TBA, SP::PSTATE,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/Disassembler/
DSparcDisassembler.cpp114 SP::TPC, SP::TNPC, SP::TSTATE, SP::TT, SP::TICK, SP::TBA, SP::PSTATE,
/external/llvm-project/llvm/lib/Target/Sparc/Disassembler/
DSparcDisassembler.cpp114 SP::TPC, SP::TNPC, SP::TSTATE, SP::TT, SP::TICK, SP::TBA, SP::PSTATE,
/external/llvm-project/lldb/source/Plugins/Instruction/ARM64/
DEmulateInstructionARM64.cpp494 case PSTATE.EL of in BranchTo()
/external/llvm/lib/Target/Sparc/AsmParser/
DSparcAsmParser.cpp1138 RegNo = Sparc::PSTATE; in matchRegisterName()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/AsmParser/
DSparcAsmParser.cpp1184 RegNo = Sparc::PSTATE; in matchRegisterName()
/external/llvm-project/llvm/lib/Target/Sparc/AsmParser/
DSparcAsmParser.cpp1195 RegNo = Sparc::PSTATE; in matchRegisterName()
/external/arm-trusted-firmware/docs/components/
Dsecure-partition-manager-mm.rst457 3. ``PSTATE``
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td1345 // Instructions to modify PSTATE, no input reg
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td1469 // Instructions to modify PSTATE, no input reg