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/external/llvm/unittests/ExecutionEngine/Orc/
DRPCUtilsTest.cpp81 Queue Q1, Q2; in TEST_F() local
82 QueueChannel C1(Q1, Q2); in TEST_F()
83 QueueChannel C2(Q2, Q1); in TEST_F()
110 Queue Q1, Q2; in TEST_F() local
111 QueueChannel C1(Q1, Q2); in TEST_F()
112 QueueChannel C2(Q2, Q1); in TEST_F()
140 Queue Q1, Q2; in TEST_F() local
141 QueueChannel C1(Q1, Q2); in TEST_F()
142 QueueChannel C2(Q2, Q1); in TEST_F()
/external/libxaac/decoder/armv7/
Dixheaacd_dec_DCT2_64_asm.s88 VLD2.32 {Q2, Q3}, [R5]!
89 VREV64.32 Q2, Q2
101 VSUB.I32 Q9, Q0, Q2
103 VADD.I32 Q8, Q0, Q2
119 VLD2.32 {Q2, Q3}, [R5]!
121 VREV64.32 Q2, Q2
148 VSUB.I32 Q9, Q0, Q2
150 VADD.I32 Q8, Q0, Q2
163 VLD2.32 {Q2, Q3}, [R5]!
165 VREV64.32 Q2, Q2
[all …]
Dixheaacd_post_twiddle_overlap.s199 VLD2.32 {Q2, Q3}, [R8]!
306 VMULL.U16 Q2, D30, D12
316 VSHR.U32 Q2, Q2, #16
319 VMLAL.S16 Q2, D31, D12
359 VQSHL.S32 Q2, Q2, Q8
362 VQSUB.S32 Q2, Q2, Q4
400 VQSHL.S32 Q2, Q2, #2
406 VQADD.S32 Q7, Q2, Q10
422 VLD2.32 {Q2, Q3}, [R8]!
562 VMULL.U16 Q2, D30, D12
[all …]
Dixheaacd_post_twiddle.s184 VMULL.U16 Q2, D18, D10
192 VSHR.U32 Q2, Q2, #16
197 VMLAL.S16 Q2, D19, D10
202 VADD.I32 Q12, Q10, Q2
292 VMULL.U16 Q2, D18, D10
300 VSHR.U32 Q2, Q2, #16
305 VMLAL.S16 Q2, D19, D10
309 VADD.I32 Q12, Q10, Q2
392 VMULL.U16 Q2, D18, D10
400 VSHR.U32 Q2, Q2, #16
[all …]
Dixheaacd_esbr_fwd_modulation.s43 VSHR.S32 Q2, Q2, #4
52 VQSUB.S32 Q4, Q0, Q2
55 VADD.S32 Q6, Q0, Q2
91 VADD.I64 Q0, Q2, Q5
Dixheaacd_no_lap1.s38 VDUP.32 Q2, R4
46 VQADD.S32 Q14, Q15, Q2
62 VQADD.S32 Q11, Q12, Q2
75 VQADD.S32 Q14, Q15, Q2
94 VQADD.S32 Q11, Q12, Q2
Dixheaacd_dct3_32.s66 VADD.I32 Q2, Q1, Q0
104 VADD.I32 Q2, Q1, Q0
159 VADD.I32 Q2, Q1, Q0
204 VADD.I32 Q2, Q1, Q0
289 VLD2.32 {Q2, Q3}, [R7]
292 VREV64.32 Q2, Q2
316 VADD.I32 Q7, Q0, Q2
318 VSUB.I32 Q6, Q0, Q2
360 VLD2.32 {Q2, Q3}, [R7]
362 VREV64.32 Q2, Q2
[all …]
Dixheaacd_esbr_cos_sin_mod_loop2.s77 VQSUB.S64 Q7, Q5, Q2
78 VQSUB.S64 Q8, Q2, Q5
108 VQSUB.S64 Q7, Q2, Q5
109 VQSUB.S64 Q8, Q5, Q2
Dixheaacd_pre_twiddle_compute.s117 VREV64.16 Q2, Q2
181 VREV64.16 Q2, Q2
247 VREV64.16 Q2, Q2
327 VREV64.16 Q2, Q2
Dixheaacd_mps_synt_pre_twiddle.s38 VMULL.S32 Q2, D0, D12
43 VSHRN.I64 D4, Q2, #31
/external/llvm-project/compiler-rt/lib/xray/
Dxray_trampoline_AArch64.S27 STP Q2, Q3, [SP, #-32]!
51 LDP Q2, Q3, [SP], #32
80 STP Q2, Q3, [SP, #-32]!
103 LDP Q2, Q3, [SP], #32
133 STP Q2, Q3, [SP, #-32]!
154 LDP Q2, Q3, [SP], #32
/external/llvm-project/llvm/test/CodeGen/AArch64/
Darm64-alloc-no-stack-realign.ll11 ; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], [sp, #32]
12 ; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], [sp]
13 ; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], {{\[}}[[BASE:x[0-9]+]], #32]
14 ; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], {{\[}}[[BASE]]]
/external/llvm/test/CodeGen/AArch64/
Darm64-alloc-no-stack-realign.ll11 ; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], [sp, #32]
12 ; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], [sp]
13 ; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], {{\[}}[[BASE:x[0-9]+]], #32]
14 ; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], {{\[}}[[BASE]]]
/external/libhevc/common/arm/
Dihevc_resi_trans_32x32_a9q.s202 VSUBL.U8 Q2,D10,D14 @ Get residue 17-24 row 2
209 VREV64.S16 Q2,Q2 @ Rev 17-24 row 2
213 VSWP D4,D5 @ Q2: 24 23 22 21 20 19 18 17 row 2
219 VADD.S16 Q9, Q13,Q2 @ e[k] = resi_tmp_1 + resi_tmp_2 k ->9-16 row 2 -- dual issue
224 VSUB.S16 Q11, Q13,Q2 @ o[k] = resi_tmp_1 - resi_tmp_2 k ->9-16 row 2 -- dual issue
231 VADD.S16 Q2, Q8, Q9 @ ee[k] = e[k] + e[16-k] k->1-8 row 2 -- dual issue
261 @ Q2 R1eee[3] R1eee[2] R2eee[3] R2eee[2] -R1eee[3] -R1eee[2] -R2eee[3] -R2eee[2]
263 VADD.S16 Q2,Q13,Q2
264 @ Q2 R1eeee[0] R1eeee[1] R2eeee[0] R2eeee[1] R1eeeo[0] R1eeeo[1] R2eeeo[0] R2eeeo[1]
266 @ Q2 R1eeee[0] R1eeee[1] R2eeee[0] R2eeee[1]
[all …]
/external/llvm/test/CodeGen/ARM/
Dcttz_vector.ll67 ; CHECK: vmov.i8 [[Q2:q[0-9]+]], #0x1
70 ; CHECK: vsub.i8 [[Q1]], [[Q1]], [[Q2]]
114 ; CHECK: vmov.i16 [[Q2:q[0-9]+]], #0x1
117 ; CHECK: vsub.i16 [[Q1]], [[Q1]], [[Q2]]
155 ; CHECK: vmov.i32 [[Q2:q[0-9]+]], #0x1
158 ; CHECK: vsub.i32 [[Q1]], [[Q1]], [[Q2]]
191 ; CHECK: vmov.i32 [[Q2:q[0-9]+]], #0x0
193 ; CHECK: vsub.i64 [[Q2]], [[Q2]], [[Q1:q[0-9]+]]
194 ; CHECK: vand [[Q1]], [[Q1]], [[Q2]]
251 ; CHECK: vmov.i8 [[Q2:q[0-9]+]], #0x1
[all …]
/external/clang/test/CodeGenCXX/
Dcopy-assign-synthesis.cpp44 Q() : Q1(30), Q2(31) {} in Q()
46 int Q2; member
48 printf("Q1 = %d Q2 = %d\n", Q1, Q2); in pr()
Dcopy-assign-synthesis-1.cpp59 Q() : Q1(30), Q2(31) {} in Q()
61 int Q2; member
63 printf("Q1 = %d Q2 = %d\n", Q1, Q2); in pr()
/external/llvm-project/clang/test/CodeGenCXX/
Dcopy-assign-synthesis.cpp44 Q() : Q1(30), Q2(31) {} in Q()
46 int Q2; member
48 printf("Q1 = %d Q2 = %d\n", Q1, Q2); in pr()
Dcopy-assign-synthesis-1.cpp59 Q() : Q1(30), Q2(31) {} in Q()
61 int Q2; member
63 printf("Q1 = %d Q2 = %d\n", Q1, Q2); in pr()
/external/llvm/lib/Target/AArch64/
DAArch64CallingConvention.td68 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
70 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
72 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
75 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
77 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
106 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
108 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
110 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
113 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
115 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>
[all …]
/external/llvm-project/llvm/test/CodeGen/ARM/
Dload_store_multiple.ll12 ;CHECK-BE: vrev64.8 [[Q1:q[0-9]+]], [[Q2:q[0-9]+]]
13 ;CHECK-BE: vrev64.8 [[Q1]], [[Q2]]
29 ;CHECK-BE: vrev64.16 [[Q1:q[0-9]+]], [[Q2:q[0-9]+]]
30 ;CHECK-BE: vrev64.16 [[Q1]], [[Q2]]
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64CallingConvention.td101 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
103 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
105 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
107 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
110 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
112 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
145 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
147 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
149 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
151 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
[all …]
/external/llvm/lib/Target/ARM/
DARMCallingConv.td75 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
82 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,
83 CCIfType<[f64], CCAssignToStackWithShadow<8, 4, [Q0, Q1, Q2, Q3]>>,
84 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 4, [Q0, Q1, Q2, Q3]>>,
94 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
138 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,
139 CCIfType<[f64], CCAssignToStackWithShadow<8, 8, [Q0, Q1, Q2, Q3]>>,
141 CCAssignToStackWithShadow<16, 16, [Q0, Q1, Q2, Q3]>>>,
142 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 8, [Q0, Q1, Q2, Q3]>>
215 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
[all …]
/external/deqp-deps/glslang/Test/
Dhlsl.gs-hs-mix.tesc97 float4 Q2 = mul(proj_matrix, float4(P2, 1.0));
109 vertex.PositionCS = Q2;
114 vertex.PositionCS = Q2;
/external/angle/third_party/vulkan-deps/glslang/src/Test/
Dhlsl.gs-hs-mix.tesc97 float4 Q2 = mul(proj_matrix, float4(P2, 1.0));
109 vertex.PositionCS = Q2;
114 vertex.PositionCS = Q2;

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